qemu-nvmm:

[Maxime Villard <max%m00nbsd.net@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Maxime Villard <max%m00nbsd.net@localhost>
Pushed By:	maxv
Date:		Sun Nov 25 15:24:56 2018 +0100
Changeset:	1cf4a4fc50079a334f087abd265658232eb09313

Modified Files:
	qemu-nvmm/distinfo
	qemu-nvmm/patches/patch-nvmm-support

Log Message:
qemu-nvmm:

 - change the include names to match those I ended up committing
 - copy only 16 XMM registers, not 32
 - synchronize RFLAGS from the exitstate
 - fix the shifts when setting segments

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=1cf4a4fc50079a334f087abd265658232eb09313

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 qemu-nvmm/distinfo                   |  2 +-
 qemu-nvmm/patches/patch-nvmm-support | 29 +++++++++++++++--------------
 2 files changed, 16 insertions(+), 15 deletions(-)

diffs:
diff --git a/qemu-nvmm/distinfo b/qemu-nvmm/distinfo
index d253dcb318..2bc1066ca6 100644
--- a/qemu-nvmm/distinfo
+++ b/qemu-nvmm/distinfo
@@ -13,5 +13,5 @@ SHA1 (patch-hw_display_omap__dss.c) = 6b13242f28e32346bc70548c216c578d98fd3420
 SHA1 (patch-hw_net_etraxfs__eth.c) = e5dd1661d60dbcd27b332403e0843500ba9544bc
 SHA1 (patch-hw_net_xilinx__axienet.c) = ebcd2676d64ce6f31e4a8c976d4fdf530ad5e8b7
 SHA1 (patch-hw_usb_dev-mtp.c) = 66543b5559d92f8e2fa9a6eb85e5dfe7c1ad3339
-SHA1 (patch-nvmm-support) = 0058ec05dfcb8bd4ebbb416fd21e40c23ec9a3c1
+SHA1 (patch-nvmm-support) = fceb3a23d5e33c25f39d33bd70e2bac788f2f57b
 SHA1 (patch-tests_Makefile.include) = 42345d697cb2e324dccf1d68bd8d61e8001c6162
diff --git a/qemu-nvmm/patches/patch-nvmm-support b/qemu-nvmm/patches/patch-nvmm-support
index e8591a533a..1b6a99f884 100644
--- a/qemu-nvmm/patches/patch-nvmm-support
+++ b/qemu-nvmm/patches/patch-nvmm-support
@@ -86,7 +86,7 @@ Add NVMM support.
 +{
 +}
 --- configure	2018-08-14 21:10:34.000000000 +0200
-+++ configure	2018-11-01 18:01:36.390800199 +0100
++++ configure	2018-11-25 07:55:31.665393888 +0100
 @@ -238,6 +238,17 @@
      return 1
  }
@@ -146,7 +146,7 @@ Add NVMM support.
  ##########################################
 +# NetBSD Virtual Machine Monitor accelerator (NVMM) check
 +if test "$nvmm" != "no" ; then
-+    if check_include "libnvmm.h" && check_include "dev/nvmm/nvmm_x86.h"; then
++    if check_include "nvmm.h"; then
 +        nvmm="yes"
 +        LIBS="-lnvmm $LIBS"
 +    else
@@ -427,8 +427,8 @@ Add NVMM support.
  obj-$(CONFIG_WHPX) += whpx-all.o
 +obj-$(CONFIG_NVMM) += nvmm-all.o
 --- target/i386/nvmm-all.c	1970-01-01 01:00:00.000000000 +0100
-+++ target/i386/nvmm-all.c	2018-11-03 13:59:52.058059097 +0100
-@@ -0,0 +1,1036 @@
++++ target/i386/nvmm-all.c	2018-11-25 15:17:50.106506876 +0100
+@@ -0,0 +1,1037 @@
 +/*
 + * Copyright (c) 2018 The NetBSD Foundation, Inc.
 + * All rights reserved.
@@ -479,8 +479,7 @@ Add NVMM support.
 +#include "qapi/error.h"
 +#include "migration/blocker.h"
 +
-+#include <libnvmm.h>
-+#include <dev/nvmm/nvmm_x86.h>
++#include <nvmm.h>
 +
 +static bool nvmm_allowed = false;
 +
@@ -517,10 +516,9 @@ Add NVMM support.
 +	nseg->selector = qseg->selector;
 +	nseg->limit = qseg->limit;
 +	nseg->base = qseg->base;
-+
 +	nseg->attrib.type =
-+	    __SHIFTOUT(attrib, DESC_S_MASK) |
-+	    __SHIFTOUT(attrib, DESC_TYPE_MASK);
++	    (__SHIFTOUT(attrib, DESC_S_MASK) << 4) |
++	    (__SHIFTOUT(attrib, DESC_TYPE_MASK) << 0);
 +	nseg->attrib.dpl = __SHIFTOUT(attrib, DESC_DPL_MASK);
 +	nseg->attrib.p = __SHIFTOUT(attrib, DESC_P_MASK);
 +	nseg->attrib.avl = __SHIFTOUT(attrib, DESC_AVL_MASK);
@@ -606,7 +604,7 @@ Add NVMM support.
 +	state.fpu.fx_mxcsr_mask = 0x0000FFFF;
 +	assert(sizeof(state.fpu.fx_87_ac) == sizeof(env->fpregs));
 +	memcpy(state.fpu.fx_87_ac, env->fpregs, sizeof(env->fpregs));
-+	for (i = 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i++) {
++	for (i = 0; i < 16; i++) {
 +		memcpy(&state.fpu.fx_xmm[i].xmm_bytes[0],
 +		    &env->xmm_regs[i].ZMM_Q(0), 8);
 +		memcpy(&state.fpu.fx_xmm[i].xmm_bytes[8],
@@ -650,8 +648,8 @@ Add NVMM support.
 +	qseg->base = nseg->base;
 +
 +	qseg->flags =
-+	    __SHIFTIN(nseg->attrib.type, DESC_S_MASK) |
-+	    __SHIFTIN(nseg->attrib.type, DESC_TYPE_MASK) |
++	    __SHIFTIN((nseg->attrib.type & 0b10000) >> 4, DESC_S_MASK) |
++	    __SHIFTIN((nseg->attrib.type & 0b01111) >> 0, DESC_TYPE_MASK) |
 +	    __SHIFTIN(nseg->attrib.dpl, DESC_DPL_MASK) |
 +	    __SHIFTIN(nseg->attrib.p, DESC_P_MASK) |
 +	    __SHIFTIN(nseg->attrib.avl, DESC_AVL_MASK) |
@@ -755,7 +753,7 @@ Add NVMM support.
 +	env->mxcsr = state.fpu.fx_mxcsr;
 +	assert(sizeof(state.fpu.fx_87_ac) == sizeof(env->fpregs));
 +	memcpy(env->fpregs, state.fpu.fx_87_ac, sizeof(env->fpregs));
-+	for (i = 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i++) {
++	for (i = 0; i < 16; i++) {
 +		memcpy(&env->xmm_regs[i].ZMM_Q(0),
 +		    &state.fpu.fx_xmm[i].xmm_bytes[0], 8);
 +		memcpy(&env->xmm_regs[i].ZMM_Q(1),
@@ -874,15 +872,18 @@ Add NVMM support.
 +}
 +
 +/*
-+ * Called after the VCPU ran. We synchronize the host view of the TPR.
++ * Called after the VCPU ran. We synchronize the host view of the TPR and
++ * RFLAGS.
 + */
 +static void
 +nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_exit *exit)
 +{
 +	struct nvmm_vcpu *vcpu = get_nvmm_vcpu(cpu);
++	struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
 +	X86CPU *x86_cpu = X86_CPU(cpu);
 +	uint64_t tpr;
 +
++	env->eflags = exit->exitstate[NVMM_X64_EXITSTATE_RFLAGS];
 +	tpr = exit->exitstate[NVMM_X64_EXITSTATE_CR8];
 +
 +	if (vcpu->tpr != tpr) {