qemu-nvmm: improvements

[Maxime Villard <max%m00nbsd.net@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Maxime Villard <max%m00nbsd.net@localhost>
Pushed By:	maxv
Date:		Sat Dec 15 15:17:07 2018 +0100
Changeset:	11a06ff8df735ca18c75c6f0b811a817dd35e57d

Modified Files:
	qemu-nvmm/distinfo
	qemu-nvmm/patches/patch-nvmm-support

Log Message:
qemu-nvmm: improvements

 - Register a RAMBlock notifier to call nvmm_hva_map().
 - Reorganize nvmm_handle_msr() a little.
 - Hide the MTRR cpuid bit, so that we don't get MTRR MSR exits.

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=11a06ff8df735ca18c75c6f0b811a817dd35e57d

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 qemu-nvmm/distinfo                   |  2 +-
 qemu-nvmm/patches/patch-nvmm-support | 63 +++++++++++++++++++++++++-----------
 2 files changed, 46 insertions(+), 19 deletions(-)

diffs:
diff --git a/qemu-nvmm/distinfo b/qemu-nvmm/distinfo
index 2bc1066ca6..814c80ce09 100644
--- a/qemu-nvmm/distinfo
+++ b/qemu-nvmm/distinfo
@@ -13,5 +13,5 @@ SHA1 (patch-hw_display_omap__dss.c) = 6b13242f28e32346bc70548c216c578d98fd3420
 SHA1 (patch-hw_net_etraxfs__eth.c) = e5dd1661d60dbcd27b332403e0843500ba9544bc
 SHA1 (patch-hw_net_xilinx__axienet.c) = ebcd2676d64ce6f31e4a8c976d4fdf530ad5e8b7
 SHA1 (patch-hw_usb_dev-mtp.c) = 66543b5559d92f8e2fa9a6eb85e5dfe7c1ad3339
-SHA1 (patch-nvmm-support) = fceb3a23d5e33c25f39d33bd70e2bac788f2f57b
+SHA1 (patch-nvmm-support) = a593635800f83081f69cb328c8abf8c0124cd74a
 SHA1 (patch-tests_Makefile.include) = 42345d697cb2e324dccf1d68bd8d61e8001c6162
diff --git a/qemu-nvmm/patches/patch-nvmm-support b/qemu-nvmm/patches/patch-nvmm-support
index 1b6a99f884..172760e153 100644
--- a/qemu-nvmm/patches/patch-nvmm-support
+++ b/qemu-nvmm/patches/patch-nvmm-support
@@ -427,8 +427,8 @@ Add NVMM support.
  obj-$(CONFIG_WHPX) += whpx-all.o
 +obj-$(CONFIG_NVMM) += nvmm-all.o
 --- target/i386/nvmm-all.c	1970-01-01 01:00:00.000000000 +0100
-+++ target/i386/nvmm-all.c	2018-11-25 15:17:50.106506876 +0100
-@@ -0,0 +1,1037 @@
++++ target/i386/nvmm-all.c	2018-12-15 14:48:22.478267925 +0100
+@@ -0,0 +1,1064 @@
 +/*
 + * Copyright (c) 2018 The NetBSD Foundation, Inc.
 + * All rights reserved.
@@ -922,39 +922,44 @@ Add NVMM support.
 +	return nvmm_assist_io(mach, vcpu->cpuid, exit, nvmm_io_callback);
 +}
 +
-+#define MSR_APICBASE		0x01b
-+
 +static int
-+nvmm_handle_msr(struct nvmm_machine *mach, struct nvmm_vcpu *vcpu,
-+    X86CPU *x86_cpu, struct nvmm_exit *exit)
++nvmm_handle_msr(struct nvmm_machine *mach, CPUState *cpu,
++    struct nvmm_exit *exit)
 +{
++	struct CPUX86State *env = (CPUArchState *)(cpu->env_ptr);
++	struct nvmm_vcpu *vcpu = get_nvmm_vcpu(cpu);
++	X86CPU *x86_cpu = X86_CPU(cpu);
 +	struct nvmm_x64_state state;
 +	uint64_t val;
 +	int ret;
 +
-+	ret = nvmm_vcpu_getstate(mach, vcpu->cpuid, &state,
-+	    NVMM_X64_STATE_GPRS);
-+	if (ret == -1) {
-+		return -1;
-+	}
++	val = exit->u.msr.val;
 +
 +	switch (exit->u.msr.msr) {
-+	case MSR_APICBASE:
++	case MSR_IA32_APICBASE:
 +		if (exit->u.msr.type == NVMM_EXIT_MSR_RDMSR) {
 +			val = cpu_get_apic_base(x86_cpu->apic_state);
-+			state.gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
-+			state.gprs[NVMM_X64_GPR_RDX] = (val >> 32);
 +		} else {
-+			val = exit->u.msr.val;
 +			cpu_set_apic_base(x86_cpu->apic_state, val);
 +		}
 +		break;
 +	default:
 +		// TODO: more MSRs to add?
-+		error_report("NVMM: Unexpected MSR %lx", exit->u.msr.msr);
++		error_report("NVMM: Unexpected MSR 0x%lx", exit->u.msr.msr);
++		return -1;
++	}
++
++	ret = nvmm_vcpu_getstate(mach, vcpu->cpuid, &state,
++	    NVMM_X64_STATE_GPRS);
++	if (ret == -1) {
 +		return -1;
 +	}
 +
++	if (exit->u.msr.type == NVMM_EXIT_MSR_RDMSR) {
++		state.gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
++		state.gprs[NVMM_X64_GPR_RDX] = (val >> 32);
++	}
++
 +	state.gprs[NVMM_X64_GPR_RIP] = exit->u.msr.npc;
 +
 +	ret = nvmm_vcpu_setstate(mach, vcpu->cpuid, &state,
@@ -1085,7 +1090,7 @@ Add NVMM support.
 +			ret = nvmm_handle_io(mach, vcpu, &exit);
 +			break;
 +		case NVMM_EXIT_MSR:
-+			ret = nvmm_handle_msr(mach, vcpu, x86_cpu, &exit);
++			ret = nvmm_handle_msr(mach, cpu, &exit);
 +			break;
 +		case NVMM_EXIT_INT_READY:
 +			vcpu->int_waiting = false;
@@ -1359,6 +1364,26 @@ Add NVMM support.
 +	.priority = 10,
 +};
 +
++static void
++nvmm_ram_block_added(RAMBlockNotifier *n, void *host, size_t size)
++{
++	struct nvmm_machine *mach = get_nvmm_mach();
++	uintptr_t hva = (uintptr_t)host;
++	int ret;
++
++	ret = nvmm_hva_map(mach, hva, size);
++
++	if (ret == -1) {
++		error_report("NVMM: Failed to map HVA, HostVA:%p "
++		    "Size:%p bytes, error=%d",
++		    (void *)hva, (void *)size, errno);
++	}
++}
++
++static struct RAMBlockNotifier nvmm_ram_notifier = {
++	.ram_block_added = nvmm_ram_block_added
++};
++
 +/* -------------------------------------------------------------------------- */
 +
 +static void
@@ -1379,10 +1404,11 @@ Add NVMM support.
 +	struct nvmm_x86_conf_cpuid cpuid;
 +	int ret;
 +
-+	/* Delete the Monitor bit, set the Hypervisor bit. */
++	/* Delete the Monitor and MTRR bits, set the Hypervisor bit. */
 +	memset(&cpuid, 0, sizeof(cpuid));
 +	cpuid.leaf = 0x00000001;
 +	cpuid.del.ecx = CPUID_EXT_MONITOR;
++	cpuid.del.edx = CPUID_MTRR;
 +	cpuid.set.ecx = CPUID_EXT_HYPERVISOR;
 +
 +	ret = nvmm_machine_configure(mach, NVMM_X86_CONF_CPUID, &cpuid);
@@ -1431,6 +1457,7 @@ Add NVMM support.
 +	}
 +
 +	memory_listener_register(&nvmm_memory_listener, &address_space_memory);
++	ram_block_notifier_add(&nvmm_ram_notifier);
 +
 +	cpu_interrupt_handler = nvmm_handle_interrupt;
 +