yosys: Update to 0.10

[Atsushi Toyokura <asteria.at%gmail.com@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Atsushi Toyokura <asteria.at%gmail.com@localhost>
Pushed By:	steleto
Date:		Wed Nov 3 22:39:29 2021 +0900
Changeset:	bd7927fe049f0761989dee06bcceca5e07633011

Modified Files:
	yosys/Makefile
	yosys/PLIST
	yosys/distinfo
Added Files:
	yosys/patches/patch-kernel_yosys.cc

Log Message:
yosys: Update to 0.10

Yosys 0.9 .. Yosys 0.10
--------------------------

 * Various
    - Added automatic gzip decompression for frontends
    - Added $_NMUX_ cell type
    - Added automatic gzip compression (based on filename extension) for backends
    - Improve attribute and parameter encoding in JSON to avoid ambiguities between
      bit vectors and strings containing [01xz]*
    - Improvements in pmgen: subpattern and recursive matches
    - Support explicit FIRRTL properties
    - Improvements in pmgen: slices, choices, define, generate
    - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
    - Added new frontend: rpc
    - Added --version and -version as aliases for -V
    - Improve yosys-smtbmc "solver not found" handling
    - Improved support of $readmem[hb] Memory Content File inclusion
    - Added CXXRTL backend
    - Use YosysHQ/abc instead of upstream berkeley-abc/abc
    - Added WASI platform support.
    - Added extmodule support to firrtl backend
    - Added $divfloor and $modfloor cells
    - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
    - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
    - Added firrtl backend support for generic parameters in blackbox components
    - Added $meminit_v2 cells (with support for write mask)
    - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
      - write priority masks, per write/write port pair
      - transparency and undefined collision behavior masks, per read/write port pair
      - read port reset and initialization
      - wide ports (accessing a naturally aligned power-of-two number of memory cells)

 * New commands and options
    - Added "write_xaiger" backend
    - Added "read_xaiger"
    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
    - Added "synth -abc9" (experimental)
    - Added "script -scriptwire"
    - Added "clkbufmap" pass
    - Added "extractinv" pass and "invertible_pin" attribute
    - Added "proc_clean -quiet"
    - Added "proc_prune" pass
    - Added "stat -tech cmos"
    - Added "opt_share" pass, run as part of "opt -full"
    - Added "-match-init" option to "dff2dffs" pass
    - Added "equiv_opt -multiclock"
    - Added "techmap_autopurge" support to techmap
    - Added "add -mod <modname[s]>"
    - Added "paramap" pass
    - Added "portlist" command
    - Added "check -mapped"
    - Added "check -allow-tbuf"
    - Added "autoname" pass
    - Added "write_verilog -extmem"
    - Added "opt_mem" pass
    - Added "scratchpad" pass
    - Added "fminit" pass
    - Added "opt_lut_ins" pass
    - Added "logger" pass
    - Added "show -nobg"
    - Added "exec" command
    - Added "design -delete"
    - Added "design -push-copy"
    - Added "qbfsat" command
    - Added "select -unset"
    - Added "dfflegalize" pass
    - Removed "opt_expr -clkinv" option, made it the default
    - Added "proc -nomux
    - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass

 * SystemVerilog
    - Added checking of always block types (always_comb, always_latch and always_ff)
    - Added support for wildcard port connections (.*)
    - Added support for enum typedefs
    - Added support for structs and packed unions.
    - Allow constant function calls in for loops and generate if and case
    - Added support for static cast
    - Added support for logic typed parameters
    - Fixed generate scoping issues
    - Added support for real-valued parameters
    - Allow localparams in constant functions
    - Module name scope support
    - Support recursive functions using ternary expressions
    - Extended support for integer types
    - Support for parameters without default values
    - Allow globals in one file to depend on globals in another
    - Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
    - Added support for parsing the 'bind' construct
    - support declaration in procedural for initialization
    - support declaration in generate for initialization
    - Support wand and wor of data types

 * Verific support
    - Added "verific -L"
    - Add Verific SVA support for "always" properties
    - Add Verific support for SVA nexttime properties
    - Improve handling of verific primitives in "verific -import -V" mode
    - Import attributes for wires
    - Support VHDL enums
    - Added support for command files

 * New back-ends
    - Added initial EFINIX support
    - Added Intel ALM: alternative synthesis for Intel FPGAs
    - Added initial Nexus support
    - Added initial MachXO2 support
    - Added initial QuickLogic PolarPro 3 support

 * ECP5 support
    - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "synth_ecp5 -abc9" (experimental)
    - Added "synth_ecp5 -nowidelut"
    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)

 * iCE40 support
    - Added "synth_ice40 -abc9" (experimental)
    - Added "synth_ice40 -device"
    - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
    - Removed "ice40_unlut"
    - Added "ice40_dsp" for Lattice iCE40 DSP packing
    - "synth_ice40 -dsp" to infer DSP blocks

 * Xilinx support
    - Added "synth_xilinx -abc9" (experimental)
    - Added "synth_xilinx -nocarry"
    - Added "synth_xilinx -nowidelut"
    - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
    - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
    - Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
    - Added "synth_xilinx -ise" (experimental)
    - Added "synth_xilinx -iopad"
    - "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
    - Added "xilinx_srl" for Xilinx shift register extraction
    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
    - Added "xilinx_dsp" for Xilinx DSP packing
    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
    - Added latch support to synth_xilinx
    - Added support for flip-flops with synchronous reset to synth_xilinx
    - Added support for flip-flops with reset and enable to synth_xilinx
    - Added "xilinx_dffopt" pass
    - Added "synth_xilinx -dff"

 * Intel support
    - Renamed labels in synth_intel (e.g. bram -> map_bram)
    - synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
    - Added "intel_alm -abc9" (experimental)

 * CoolRunner2 support
    - Separate and improve buffer cell insertion pass
    - Use extract_counter to optimize counters

Yosys 0.8 .. Yosys 0.9
----------------------

 * Various
    - Many bugfixes and small improvements
    - Added support for SystemVerilog interfaces and modports
    - Added "write_edif -attrprop"
    - Added "opt_lut" pass
    - Added "gate2lut.v" techmap rule
    - Added "rename -src"
    - Added "equiv_opt" pass
    - Added "flowmap" LUT mapping pass
    - Added "rename -wire" to rename cells based on the wires they drive
    - Added "bugpoint" for creating minimised testcases
    - Added "write_edif -gndvccy"
    - "write_verilog" to escape Verilog keywords
    - Fixed sign handling of real constants
    - "write_verilog" to write initial statement for initial flop state
    - Added pmgen pattern matcher generator
    - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
    - Added "setundef -params" to replace undefined cell parameters
    - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
    - Fixed handling of defparam when default_nettype is none
    - Fixed "wreduce" flipflop handling
    - Fixed FIRRTL to Verilog process instance subfield assignment
    - Added "write_verilog -siminit"
    - Several fixes and improvements for mem2reg memories
    - Fixed handling of task output ports in clocked always blocks
    - Improved handling of and-with-1 and or-with-0 in "opt_expr"
    - Added "read_aiger" frontend
    - Added "mutate" pass
    - Added "hdlname" attribute
    - Added "rename -output"
    - Added "read_ilang -lib"
    - Improved "proc" full_case detection and handling
    - Added "whitebox" and "lib_whitebox" attributes
    - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
    - Added Python bindings and support for Python plug-ins
    - Added "pmux2shiftx"
    - Added log_debug framework for reduced default verbosity
    - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
    - Added "peepopt" peephole optimisation pass using pmgen
    - Added approximate support for SystemVerilog "var" keyword
    - Added parsing of "specify" blocks into $specrule and $specify[23]
    - Added support for attributes on parameters and localparams
    - Added support for parsing attributes on port connections
    - Added "wreduce -keepdc"
    - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
    - Added Verilog wand/wor wire type support
    - Added support for elaboration system tasks
    - Added "muxcover -mux{4,8,16}=<cost>"
    - Added "muxcover -dmux=<cost>"
    - Added "muxcover -nopartial"
    - Added "muxpack" pass
    - Added "pmux2shiftx -norange"
    - Added support for "~" in filename parsing
    - Added "read_verilog -pwires" feature to turn parameters into wires
    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
    - Fixed genvar to be a signed type
    - Added support for attributes on case rules
    - Added "upto" and "offset" to JSON frontend and backend
    - Several liberty file parser improvements
    - Fixed handling of more complex BRAM patterns
    - Add "write_aiger -I -O -B"

 * Formal Verification
    - Added $changed support to read_verilog
    - Added "read_verilog -noassert -noassume -assert-assumes"
    - Added btor ops for $mul, $div, $mod and $concat
    - Added yosys-smtbmc support for btor witnesses
    - Added "supercover" pass
    - Fixed $global_clock handling vs autowire
    - Added $dffsr support to "async2sync"
    - Added "fmcombine" pass
    - Added memory init support in "write_btor"
    - Added "cutpoint" pass
    - Changed "ne" to "neq" in btor2 output
    - Added support for SVA "final" keyword
    - Added "fmcombine -initeq -anyeq"
    - Added timescale and generated-by header to yosys-smtbmc vcd output
    - Improved BTOR2 handling of undriven wires

 * Verific support
    - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
    - Improved support for asymmetric memories
    - Added "verific -chparam"
    - Fixed "verific -extnets" for more complex situations
    - Added "read -verific" and "read -noverific"
    - Added "hierarchy -chparam"

 * New back-ends
    - Added initial Anlogic support
    - Added initial SmartFusion2 and IGLOO2 support

 * ECP5 support
    - Added "synth_ecp5 -nowidelut"
    - Added BRAM inference support to "synth_ecp5"
    - Added support for transforming Diamond IO and flipflop primitives

 * iCE40 support
    - Added "ice40_unlut" pass
    - Added "synth_ice40 -relut"
    - Added "synth_ice40 -noabc"
    - Added "synth_ice40 -dffe_min_ce_use"
    - Added DSP inference support using pmgen
    - Added support for initialising BRAM primitives from a file
    - Added iCE40 Ultra RGB LED driver cells

 * Xilinx support
    - Use "write_edif -pvector bra" for Xilinx EDIF files
    - Fixes for VPR place and route support with "synth_xilinx"
    - Added more cell simulation models
    - Added "synth_xilinx -family"
    - Added "stat -tech xilinx" to estimate logic cell usage
    - Added "synth_xilinx -nocarry"
    - Added "synth_xilinx -nowidelut"
    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
    - Added support for mapping RAM32X1D

Yosys 0.7 .. Yosys 0.8
----------------------

 * Various
    - Many bugfixes and small improvements
    - Strip debug symbols from installed binary
    - Replace -ignore_redef with -[no]overwrite in front-ends
    - Added write_verilog hex dump support, add -nohex option
    - Added "write_verilog -decimal"
    - Added "scc -set_attr"
    - Added "verilog_defines" command
    - Remember defines from one read_verilog to next
    - Added support for hierarchical defparam
    - Added FIRRTL back-end
    - Improved ABC default scripts
    - Added "design -reset-vlog"
    - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
    - Added Verilog $rtoi and $itor support
    - Added "check -initdrv"
    - Added "read_blif -wideports"
    - Added support for SystemVerilog "++" and "--" operators
    - Added support for SystemVerilog unique, unique0, and priority case
    - Added "write_edif" options for edif "flavors"
    - Added support for resetall compiler directive
    - Added simple C beck-end (bitwise combinatorical only atm)
    - Added $_ANDNOT_ and $_ORNOT_ cell types
    - Added cell library aliases to "abc -g"
    - Added "setundef -anyseq"
    - Added "chtype" command
    - Added "design -import"
    - Added "write_table" command
    - Added "read_json" command
    - Added "sim" command
    - Added "extract_fa" and "extract_reduce" commands
    - Added "extract_counter" command
    - Added "opt_demorgan" command
    - Added support for $size and $bits SystemVerilog functions
    - Added "blackbox" command
    - Added "ltp" command
    - Added support for editline as replacement for readline
    - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
    - Added "yosys -E" for creating Makefile dependencies files
    - Added "synth -noshare"
    - Added "memory_nordff"
    - Added "setundef -undef -expose -anyconst"
    - Added "expose -input"
    - Added specify/specparam parser support (simply ignore them)
    - Added "write_blif -inames -iattr"
    - Added "hierarchy -simcheck"
    - Added an option to statically link abc into yosys
    - Added protobuf back-end
    - Added BLIF parsing support for .conn and .cname
    - Added read_verilog error checking for reg/wire/logic misuse
    - Added "make coverage" and ENABLE_GCOV build option

 * Changes in Yosys APIs
    - Added ConstEval defaultval feature
    - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
    - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
    - Added log_file_warning() and log_file_error() functions

 * Formal Verification
    - Added "write_aiger"
    - Added "yosys-smtbmc --aig"
    - Added "always <positive_int>" to .smtc format
    - Added $cover cell type and support for cover properties
    - Added $fair/$live cell type and support for liveness properties
    - Added smtbmc support for memory vcd dumping
    - Added "chformal" command
    - Added "write_smt2 -stbv" and "write_smt2 -stdt"
    - Fix equiv_simple, old behavior now available with "equiv_simple -short"
    - Change to Yices2 as default SMT solver (it is GPL now)
    - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
    - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
    - Added a brand new "write_btor" command for BTOR2
    - Added clk2fflogic memory support and other improvements
    - Added "async memory write" support to write_smt2
    - Simulate clock toggling in yosys-smtbmc VCD output
    - Added $allseq/$allconst cells for EA-solving
    - Make -nordff the default in "prep"
    - Added (* gclk *) attribute
    - Added "async2sync" pass for single-clock designs with async resets

 * Verific support
    - Many improvements in Verific front-end
    - Added proper handling of concurent SVA properties
    - Map "const" and "rand const" to $anyseq/$anyconst
    - Added "verific -import -flatten" and "verific -import -extnets"
    - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
    - Remove PSL support (because PSL has been removed in upstream Verific)
    - Improve integration with "hierarchy" command design elaboration
    - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
    - Added simpilied "read" command that automatically uses verific if available
    - Added "verific -set-<severity> <msg_id>.."
    - Added "verific -work <libname>"

 * New back-ends
    - Added initial Coolrunner-II support
    - Added initial eASIC support
    - Added initial ECP5 support

 * GreenPAK Support
    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.

 * iCE40 Support
    - Add "synth_ice40 -vpr"
    - Add "synth_ice40 -nodffe"
    - Add "synth_ice40 -json"
    - Add Support for UltraPlus cells

 * MAX10 and Cyclone IV Support
    - Added initial version of metacommand "synth_intel".
    - Improved write_verilog command to produce VQM netlist for Quartus Prime.
    - Added support for MAX10 FPGA family synthesis.
    - Added support for Cyclone IV family synthesis.
    - Added example of implementation for DE2i-150 board.
    - Added example of implementation for MAX10 development kit.
    - Added LFSR example from Asic World.
    - Added "dffinit -highlow" for mapping to Intel primitives

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=bd7927fe049f0761989dee06bcceca5e07633011

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 yosys/Makefile                      |  42 ++++++---
 yosys/PLIST                         | 176 ++++++++++++++++++++++++++++++++++--
 yosys/distinfo                      |   7 +-
 yosys/patches/patch-kernel_yosys.cc |  38 ++++++++
 4 files changed, 239 insertions(+), 24 deletions(-)

diffs:
diff --git a/yosys/Makefile b/yosys/Makefile
index d5b6a2242c..0013bb9d69 100644
--- a/yosys/Makefile
+++ b/yosys/Makefile
@@ -1,50 +1,66 @@
 # $NetBSD$
 
-DISTNAME=	yosys-a44cc7a
+GITHUB_PROJECT=	yosys
+GITHUB_TAG=	refs/tags/${DISTNAME}
+DISTNAME=	yosys-0.10
 CATEGORIES=	devel
-MASTER_SITES=	${MASTER_SITE_GITHUB:=cliffordwolf/}
-GITHUB_TAG=	69468d5a16f87616af9c7f084f6ff247f3513050
+MASTER_SITES=	${MASTER_SITE_GITHUB:=YosysHQ/}
 
 MAINTAINER=	pkgsrc-users%NetBSD.org@localhost
 HOMEPAGE=	https://github.com/cliffordwolf/
-COMMENT=	Yosys is a framework for Verilog RTL synthesis
+COMMENT=	Framework for Verilog RTL synthesis
 LICENSE=	isc
 
 USE_LANGUAGES+=			c c++
 USE_TOOLS+=			gmake pkg-config bison gawk flex
 PYTHON_VERSIONS_INCOMPATIBLE=	27
-PKGCONFIG_CONFIG=		${PKG_CONFIG:Q}
-DEPENDS+=			mercurial-[0-9]*:../../devel/mercurial
+# PKGCONFIG_CONFIG=		${PKG_CONFIG:Q}
 
-WRKSRC=			${WRKDIR}/yosys-${GITHUB_TAG}
+WRKSRC=			${WRKDIR}/yosys-${DISTNAME}
 
 SUBST_CLASSES+=		python3
 SUBST_MESSAGE.python3=	Fixing non-shellbang references to python3.
 SUBST_STAGE.python3=	pre-configure
 SUBST_SED.python3=	-e 's,python3,${PYTHONBIN},g'
-SUBST_FILES.python3+=	techlibs/common/Makefile.inc
-SUBST_FILES.python3+=	techlibs/ice40/Makefile.inc
-SUBST_FILES.python3+=	techlibs/xilinx/Makefile.inc
+SUBST_FILES.python3+=	Makefile
+SUBST_FILES.python3+=	backends/smt2/Makefile.inc
+SUBST_FILES.python3+=	techlibs/gowin/Makefile.inc
 SUBST_FILES.python3+=	tests/bram/run-test.sh
 SUBST_FILES.python3+=	tests/fsm/run-test.sh
+SUBST_FILES.python3+=	tests/opt_share/run-test.sh
 SUBST_FILES.python3+=	tests/realmath/run-test.sh
+SUBST_FILES.python3+=	tests/rpc/exec.ys
+SUBST_FILES.python3+=	tests/rpc/run-test.sh
 SUBST_FILES.python3+=	tests/share/run-test.sh
 
-
 SUBST_CLASSES+=		python
 SUBST_MESSAGE.python=	Fixing shellbang references to python3.
 SUBST_STAGE.python=	pre-configure
-SUBST_SED.python=	-e 's,/usr/bin/env\ python3,${PYTHONBIN},g'
-SUBST_FILES.python=	backends/smt2/smtbmc.py
+SUBST_SED.python=	-e 's,/usr/bin/env python3,${PYTHONBIN},g'
+SUBST_FILES.python=	backends/edif/runtest.py
+SUBST_FILES.python+=	backends/smt2/smtbmc.py
+SUBST_FILES.python+=	passes/pmgen/pmgen.py
 SUBST_FILES.python+=	techlibs/common/cellhelp.py
+SUBST_FILES.python+=	techlibs/ecp5/brams_connect.py
+SUBST_FILES.python+=	techlibs/ecp5/brams_init.py
+SUBST_FILES.python+=	techlibs/gowin/brams_init.py
 SUBST_FILES.python+=	techlibs/ice40/brams_init.py
+SUBST_FILES.python+=	techlibs/nexus/cells_xtra.py
 SUBST_FILES.python+=	techlibs/xilinx/brams_init.py
+SUBST_FILES.python+=	techlibs/xilinx/cells_xtra.py
 SUBST_FILES.python+=	tests/bram/generate.py
 SUBST_FILES.python+=	tests/fsm/generate.py
+SUBST_FILES.python+=	tests/opt_share/generate.py
 SUBST_FILES.python+=	tests/realmath/generate.py
 SUBST_FILES.python+=	tests/share/generate.py
 SUBST_FILES.python+=	tests/tools/txt2tikztiming.py
 
+.include "../../mk/bsd.prefs.mk"
+
+.if ${OPSYS} != "Linux"
+BUILDLINK_TRANSFORM=	rm:-ldl
+.endif
+
 .include "../../lang/python/pyversion.mk"
 .include "../../lang/tcl/buildlink3.mk"
 .include "../../devel/readline/buildlink3.mk"
diff --git a/yosys/PLIST b/yosys/PLIST
index 409ea5c36f..a58097f743 100644
--- a/yosys/PLIST
+++ b/yosys/PLIST
@@ -4,14 +4,73 @@ bin/yosys-abc
 bin/yosys-config
 bin/yosys-filterlib
 bin/yosys-smtbmc
+share/yosys/abc9_map.v
+share/yosys/abc9_model.v
+share/yosys/abc9_unmap.v
+share/yosys/achronix/speedster22i/cells_map.v
+share/yosys/achronix/speedster22i/cells_sim.v
 share/yosys/adff2dff.v
+share/yosys/anlogic/arith_map.v
+share/yosys/anlogic/cells_map.v
+share/yosys/anlogic/cells_sim.v
+share/yosys/anlogic/eagle_bb.v
+share/yosys/anlogic/lutram_init_16x4.vh
+share/yosys/anlogic/lutrams.txt
+share/yosys/anlogic/lutrams_map.v
 share/yosys/cells.lib
+share/yosys/cmp2lcu.v
+share/yosys/cmp2lut.v
+share/yosys/coolrunner2/cells_counter_map.v
+share/yosys/coolrunner2/cells_latch.v
+share/yosys/coolrunner2/cells_sim.v
+share/yosys/coolrunner2/tff_extract.v
+share/yosys/coolrunner2/xc2_dff.lib
+share/yosys/dff2ff.v
+share/yosys/ecp5/arith_map.v
+share/yosys/ecp5/bram_conn_1.vh
+share/yosys/ecp5/bram_conn_18.vh
+share/yosys/ecp5/bram_conn_2.vh
+share/yosys/ecp5/bram_conn_36.vh
+share/yosys/ecp5/bram_conn_4.vh
+share/yosys/ecp5/bram_conn_9.vh
+share/yosys/ecp5/bram_init_1_2_4.vh
+share/yosys/ecp5/bram_init_9_18_36.vh
+share/yosys/ecp5/brams.txt
+share/yosys/ecp5/brams_map.v
+share/yosys/ecp5/cells_bb.v
+share/yosys/ecp5/cells_ff.vh
+share/yosys/ecp5/cells_io.vh
+share/yosys/ecp5/cells_map.v
+share/yosys/ecp5/cells_sim.v
+share/yosys/ecp5/dsp_map.v
+share/yosys/ecp5/latches_map.v
+share/yosys/ecp5/lutrams.txt
+share/yosys/ecp5/lutrams_map.v
+share/yosys/efinix/arith_map.v
+share/yosys/efinix/brams.txt
+share/yosys/efinix/brams_map.v
+share/yosys/efinix/cells_map.v
+share/yosys/efinix/cells_sim.v
+share/yosys/efinix/gbuf_map.v
+share/yosys/gate2lut.v
+share/yosys/gowin/arith_map.v
+share/yosys/gowin/bram_init_16.vh
+share/yosys/gowin/brams.txt
+share/yosys/gowin/brams_init3.vh
+share/yosys/gowin/brams_map.v
 share/yosys/gowin/cells_map.v
 share/yosys/gowin/cells_sim.v
+share/yosys/gowin/lutrams.txt
+share/yosys/gowin/lutrams_map.v
+share/yosys/greenpak4/cells_blackbox.v
 share/yosys/greenpak4/cells_latch.v
 share/yosys/greenpak4/cells_map.v
 share/yosys/greenpak4/cells_sim.v
+share/yosys/greenpak4/cells_sim_ams.v
+share/yosys/greenpak4/cells_sim_digital.v
+share/yosys/greenpak4/cells_sim_wip.v
 share/yosys/greenpak4/gp_dff.lib
+share/yosys/ice40/abc9_model.v
 share/yosys/ice40/arith_map.v
 share/yosys/ice40/brams.txt
 share/yosys/ice40/brams_init1.vh
@@ -20,16 +79,32 @@ share/yosys/ice40/brams_init3.vh
 share/yosys/ice40/brams_map.v
 share/yosys/ice40/cells_map.v
 share/yosys/ice40/cells_sim.v
+share/yosys/ice40/dsp_map.v
+share/yosys/ice40/ff_map.v
 share/yosys/ice40/latches_map.v
-share/yosys/include/backends/ilang/ilang_backend.h
+share/yosys/include/backends/cxxrtl/cxxrtl.h
+share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
+share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd.h
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
+share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.h
+share/yosys/include/backends/rtlil/rtlil_backend.h
 share/yosys/include/frontends/ast/ast.h
+share/yosys/include/frontends/ast/ast_binding.h
+share/yosys/include/frontends/blif/blifparse.h
+share/yosys/include/kernel/binding.h
 share/yosys/include/kernel/celledges.h
 share/yosys/include/kernel/celltypes.h
 share/yosys/include/kernel/consteval.h
+share/yosys/include/kernel/constids.inc
+share/yosys/include/kernel/ff.h
+share/yosys/include/kernel/ffinit.h
 share/yosys/include/kernel/hashlib.h
 share/yosys/include/kernel/log.h
 share/yosys/include/kernel/macc.h
+share/yosys/include/kernel/mem.h
 share/yosys/include/kernel/modtools.h
+share/yosys/include/kernel/qcsat.h
 share/yosys/include/kernel/register.h
 share/yosys/include/kernel/rtlil.h
 share/yosys/include/kernel/satgen.h
@@ -38,24 +113,109 @@ share/yosys/include/kernel/utils.h
 share/yosys/include/kernel/yosys.h
 share/yosys/include/libs/ezsat/ezminisat.h
 share/yosys/include/libs/ezsat/ezsat.h
+share/yosys/include/libs/json11/json11.hpp
 share/yosys/include/libs/sha1/sha1.h
 share/yosys/include/passes/fsm/fsmdata.h
+share/yosys/intel/common/altpll_bb.v
+share/yosys/intel/common/brams_m9k.txt
+share/yosys/intel/common/brams_map_m9k.v
+share/yosys/intel/common/ff_map.v
+share/yosys/intel/common/m9k_bb.v
+share/yosys/intel/cyclone10lp/cells_map.v
+share/yosys/intel/cyclone10lp/cells_sim.v
+share/yosys/intel/cycloneiv/cells_map.v
+share/yosys/intel/cycloneiv/cells_sim.v
+share/yosys/intel/cycloneive/cells_map.v
+share/yosys/intel/cycloneive/cells_sim.v
+share/yosys/intel/max10/cells_map.v
+share/yosys/intel/max10/cells_sim.v
+share/yosys/intel_alm/common/abc9_map.v
+share/yosys/intel_alm/common/abc9_model.v
+share/yosys/intel_alm/common/abc9_unmap.v
+share/yosys/intel_alm/common/alm_map.v
+share/yosys/intel_alm/common/alm_sim.v
+share/yosys/intel_alm/common/arith_alm_map.v
+share/yosys/intel_alm/common/bram_m10k.txt
+share/yosys/intel_alm/common/bram_m20k.txt
+share/yosys/intel_alm/common/bram_m20k_map.v
+share/yosys/intel_alm/common/dff_map.v
+share/yosys/intel_alm/common/dff_sim.v
+share/yosys/intel_alm/common/dsp_map.v
+share/yosys/intel_alm/common/dsp_sim.v
+share/yosys/intel_alm/common/lutram_mlab.txt
+share/yosys/intel_alm/common/megafunction_bb.v
+share/yosys/intel_alm/common/mem_sim.v
+share/yosys/intel_alm/common/misc_sim.v
+share/yosys/intel_alm/common/quartus_rename.v
+share/yosys/intel_alm/cyclonev/cells_sim.v
+share/yosys/machxo2/cells_map.v
+share/yosys/machxo2/cells_sim.v
+share/yosys/mul2dsp.v
+share/yosys/nexus/arith_map.v
+share/yosys/nexus/brams.txt
+share/yosys/nexus/brams_init.vh
+share/yosys/nexus/brams_map.v
+share/yosys/nexus/cells_map.v
+share/yosys/nexus/cells_sim.v
+share/yosys/nexus/cells_xtra.v
+share/yosys/nexus/dsp_map.v
+share/yosys/nexus/latches_map.v
+share/yosys/nexus/lrams.txt
+share/yosys/nexus/lrams_init.vh
+share/yosys/nexus/lrams_map.v
+share/yosys/nexus/lutrams.txt
+share/yosys/nexus/lutrams_map.v
+share/yosys/nexus/parse_init.vh
 share/yosys/pmux2mux.v
-share/yosys/python3/smtio.py
+share/yosys/quicklogic/abc9_map.v
+share/yosys/quicklogic/abc9_model.v
+share/yosys/quicklogic/abc9_unmap.v
+share/yosys/quicklogic/cells_sim.v
+share/yosys/quicklogic/lut_sim.v
+share/yosys/quicklogic/pp3_cells_map.v
+share/yosys/quicklogic/pp3_cells_sim.v
+share/yosys/quicklogic/pp3_ffs_map.v
+share/yosys/quicklogic/pp3_latches_map.v
+share/yosys/quicklogic/pp3_lut_map.v
+share/yosys/sf2/arith_map.v
+share/yosys/sf2/cells_map.v
+share/yosys/sf2/cells_sim.v
 share/yosys/simcells.v
 share/yosys/simlib.v
 share/yosys/techmap.v
+share/yosys/usr/pkg/bin/python3.8/smtio.py
+share/yosys/xilinx/abc9_model.v
 share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/brams.txt
-share/yosys/xilinx/brams_bb.v
 share/yosys/xilinx/brams_init_16.vh
 share/yosys/xilinx/brams_init_18.vh
 share/yosys/xilinx/brams_init_32.vh
 share/yosys/xilinx/brams_init_36.vh
-share/yosys/xilinx/brams_map.v
+share/yosys/xilinx/brams_init_8.vh
+share/yosys/xilinx/brams_init_9.vh
 share/yosys/xilinx/cells_map.v
 share/yosys/xilinx/cells_sim.v
 share/yosys/xilinx/cells_xtra.v
-share/yosys/xilinx/drams.txt
-share/yosys/xilinx/drams_bb.v
-share/yosys/xilinx/drams_map.v
+share/yosys/xilinx/ff_map.v
+share/yosys/xilinx/lut4_lutrams.txt
+share/yosys/xilinx/lut6_lutrams.txt
+share/yosys/xilinx/lut_map.v
+share/yosys/xilinx/lutrams_map.v
+share/yosys/xilinx/mux_map.v
+share/yosys/xilinx/xc2v_brams.txt
+share/yosys/xilinx/xc2v_brams_map.v
+share/yosys/xilinx/xc3s_mult_map.v
+share/yosys/xilinx/xc3sa_brams.txt
+share/yosys/xilinx/xc3sda_brams.txt
+share/yosys/xilinx/xc3sda_dsp_map.v
+share/yosys/xilinx/xc4v_dsp_map.v
+share/yosys/xilinx/xc5v_dsp_map.v
+share/yosys/xilinx/xc6s_brams.txt
+share/yosys/xilinx/xc6s_brams_map.v
+share/yosys/xilinx/xc6s_dsp_map.v
+share/yosys/xilinx/xc7_brams_map.v
+share/yosys/xilinx/xc7_dsp_map.v
+share/yosys/xilinx/xc7_xcu_brams.txt
+share/yosys/xilinx/xcu_brams_map.v
+share/yosys/xilinx/xcu_dsp_map.v
+share/yosys/xilinx/xcup_urams.txt
+share/yosys/xilinx/xcup_urams_map.v
diff --git a/yosys/distinfo b/yosys/distinfo
index d0992b55c1..4b56aec9f6 100644
--- a/yosys/distinfo
+++ b/yosys/distinfo
@@ -1,5 +1,6 @@
 $NetBSD$
 
-RMD160 (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = d1323bbd2795c21bc8cfb369371f5f482906c896
-SHA512 (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = 10f298a99dd64635f49621f925bfee8f35545e449b0e4fb5dc76f3fc62adcf30862345aeaf4e1e7ef4b0499c8c3240928608b2b33d6c900ca89b04e6f536bc13
-Size (yosys-a44cc7a-69468d5a16f87616af9c7f084f6ff247f3513050.tar.gz) = 981426 bytes
+BLAKE2s (yosys-0.10.tar.gz) = 94ebc7b69ef97fb162cae500e8c74fac4dd71b1169acd2eb68a10c49f669c93a
+SHA512 (yosys-0.10.tar.gz) = 2168a206d4395fd83649a04ddfa717ddc4509b171da859979f4ba3eb61a350d4f5110439503651dfe24cc6860935a77c465000b047bd806a73a6657da331b52a
+Size (yosys-0.10.tar.gz) = 2020669 bytes
+SHA1 (patch-kernel_yosys.cc) = 81e504f0a61baa47eca7cec021ae60d8ed432e3b
diff --git a/yosys/patches/patch-kernel_yosys.cc b/yosys/patches/patch-kernel_yosys.cc
new file mode 100644
index 0000000000..0433af4440
--- /dev/null
+++ b/yosys/patches/patch-kernel_yosys.cc
@@ -0,0 +1,38 @@
+$NetBSD$
+
+support NetBSD
+
+--- kernel/yosys.cc.orig	2021-11-01 14:44:53.161071165 +0000
++++ kernel/yosys.cc
+@@ -55,7 +55,7 @@
+ #  include <glob.h>
+ #endif
+ 
+-#ifdef __FreeBSD__
++#if defined(__FreeBSD__) || defined(__NetBSD__)
+ #  include <sys/sysctl.h>
+ #endif
+ 
+@@ -790,6 +790,22 @@ std::string proc_self_dirname()
+ 	free(buffer);
+ 	return path;
+ }
++#elif defined(__NetBSD__)
++std::string proc_self_dirname()
++{
++	const int mib[4] = {CTL_KERN, KERN_PROC_ARGS, -1, KERN_PROC_PATHNAME};
++	char *buffer;
++	size_t buflen;
++	std::string path;
++	buffer = (char *)asysctl(mib, 4, &buflen);
++	if (buffer == NULL)
++		log_error("sysctl failed: %s\n", strerror(errno));
++	while (buflen > 0 && buffer[buflen-1] != '/')
++		buflen--;
++	path.assign(buffer, buflen);
++	free(buffer);
++	return path;
++}
+ #elif defined(__APPLE__)
+ std::string proc_self_dirname()
+ {