yosys: Update to 0.12

[Atsushi Toyokura <asteria.at%gmail.com@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Atsushi Toyokura <asteria.at%gmail.com@localhost>
Pushed By:	steleto
Date:		Sat Dec 11 16:29:04 2021 +0900
Changeset:	3fe52f3b7711ced42091e4f091cd9cb541d529c9

Modified Files:
	yosys/Makefile
	yosys/PLIST
	yosys/distinfo

Log Message:
yosys: Update to 0.12

Yosys 0.11 .. Yosys 0.12
--------------------------

 * Various
    - Added iopadmap native support for negative-polarity output enable
    - ABC update

 * SystemVerilog
    - Support parameters using struct as a wiretype

 * New commands and options
    - Added "-genlib" option to "abc" pass
    - Added "sta" very crude static timing analysis pass

 * Verific support
    - Fixed memory block size in import

 * New back-ends
    - Added support for GateMate FPGA from Cologne Chip AG

 * Intel ALM support
    - Added preliminary Arria V support

Yosys 0.10 .. Yosys 0.11
--------------------------

 * Various
    - Added $aldff and $aldffe (flip-flops with async load) cells

 * SystemVerilog
    - Fixed an issue which prevented writing directly to a memory word via a
      connection to an output port
    - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
      filling the width of a cell input
    - Fixed an issue where connecting a slice covering the entirety of a signed
      signal to a cell input would cause a failed assertion

 * Verific support
    - Importer support for {PRIM,WIDE_OPER}_DFF
    - Importer support for PRIM_BUFIF1
    - Option to use Verific without VHDL support
    - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
    - Added -cfg option for getting/setting Verific runtime flags

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=3fe52f3b7711ced42091e4f091cd9cb541d529c9

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 yosys/Makefile |  4 ++--
 yosys/PLIST    | 11 +++++++++++
 yosys/distinfo |  6 +++---
 3 files changed, 16 insertions(+), 5 deletions(-)

diffs:
diff --git a/yosys/Makefile b/yosys/Makefile
index b5ec708b57..c8e1b1da82 100644
--- a/yosys/Makefile
+++ b/yosys/Makefile
@@ -2,12 +2,12 @@
 
 GITHUB_PROJECT=	yosys
 GITHUB_TAG=	refs/tags/${DISTNAME}
-DISTNAME=	yosys-0.10
+DISTNAME=	yosys-0.12
 CATEGORIES=	devel
 MASTER_SITES=	${MASTER_SITE_GITHUB:=YosysHQ/}
 
 MAINTAINER=	pkgsrc-users%NetBSD.org@localhost
-HOMEPAGE=	https://github.com/cliffordwolf/
+HOMEPAGE=	https://yosyshq.net/yosys/
 COMMENT=	Framework for Verilog RTL synthesis
 LICENSE=	isc
 
diff --git a/yosys/PLIST b/yosys/PLIST
index c7c1bcdd48..36acc7376b 100644
--- a/yosys/PLIST
+++ b/yosys/PLIST
@@ -53,6 +53,17 @@ share/yosys/efinix/cells_map.v
 share/yosys/efinix/cells_sim.v
 share/yosys/efinix/gbuf_map.v
 share/yosys/gate2lut.v
+share/yosys/gatemate/arith_map.v
+share/yosys/gatemate/brams.txt
+share/yosys/gatemate/brams_init_20.vh
+share/yosys/gatemate/brams_init_40.vh
+share/yosys/gatemate/brams_map.v
+share/yosys/gatemate/cells_bb.v
+share/yosys/gatemate/cells_sim.v
+share/yosys/gatemate/lut_map.v
+share/yosys/gatemate/mul_map.v
+share/yosys/gatemate/mux_map.v
+share/yosys/gatemate/reg_map.v
 share/yosys/gowin/arith_map.v
 share/yosys/gowin/bram_init_16.vh
 share/yosys/gowin/brams.txt
diff --git a/yosys/distinfo b/yosys/distinfo
index 4b56aec9f6..95b1992c43 100644
--- a/yosys/distinfo
+++ b/yosys/distinfo
@@ -1,6 +1,6 @@
 $NetBSD$
 
-BLAKE2s (yosys-0.10.tar.gz) = 94ebc7b69ef97fb162cae500e8c74fac4dd71b1169acd2eb68a10c49f669c93a
-SHA512 (yosys-0.10.tar.gz) = 2168a206d4395fd83649a04ddfa717ddc4509b171da859979f4ba3eb61a350d4f5110439503651dfe24cc6860935a77c465000b047bd806a73a6657da331b52a
-Size (yosys-0.10.tar.gz) = 2020669 bytes
+BLAKE2s (yosys-0.12.tar.gz) = d9b850db3619ce0cb3a9d0e5a15a2cc0aa51bce5c01320a193062e99fadc4f64
+SHA512 (yosys-0.12.tar.gz) = df91ea75ae08c7c7e134cfa6284c4e9349e6f85f2df32e4710a571176d5e1a334a6e1e77d52bf573686d33b405559e40af1a8d42cbd4e1f95f0e3b4e212e0b06
+Size (yosys-0.12.tar.gz) = 2060970 bytes
 SHA1 (patch-kernel_yosys.cc) = 81e504f0a61baa47eca7cec021ae60d8ed432e3b