yosys: remove, pkgsrc version is newer

To: pkgsrc-wip-changes%NetBSD.org@localhost
Subject: yosys: remove, pkgsrc version is newer
From: Thomas Klausner <wiz%NetBSD.org@localhost>
Date: Wed, 27 Mar 2024 22:38:30 +0000
Module Name:	pkgsrc-wip
Committed By:	Thomas Klausner <wiz%NetBSD.org@localhost>
Pushed By:	wiz
Date:		Wed Mar 27 23:38:30 2024 +0100
Changeset:	abb5cc594233ff5f2549aae49f86601ae72f792a

Modified Files:
	Makefile
Removed Files:
	yosys/DESCR
	yosys/Makefile
	yosys/PLIST
	yosys/distinfo
	yosys/patches/patch-kernel_yosys.cc

Log Message:
yosys: remove, pkgsrc version is newer

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=abb5cc594233ff5f2549aae49f86601ae72f792a

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 Makefile                            |   3 +-
 yosys/DESCR                         |   2 -
 yosys/Makefile                      |  83 ------------
 yosys/PLIST                         | 262 ------------------------------------
 yosys/distinfo                      |   6 -
 yosys/patches/patch-kernel_yosys.cc |  38 ------
 6 files changed, 2 insertions(+), 392 deletions(-)

diffs:
diff --git a/Makefile b/Makefile
index 737d16261e..7ce28a9082 100644
--- a/Makefile
+++ b/Makefile
@@ -98,6 +98,7 @@ SUBDIR+=	WEPCrack
 SUBDIR+=	ZMusic
 SUBDIR+=	ZenNode
 SUBDIR+=	a2ps-sharatype
+SUBDIR+=	abcl
 SUBDIR+=	accountsservice
 SUBDIR+=	acl
 SUBDIR+=	acme-client
@@ -1415,6 +1416,7 @@ SUBDIR+=	heroes
 SUBDIR+=	herwig
 SUBDIR+=	hey
 SUBDIR+=	hgsubversion
+SUBDIR+=	hiawatha
 SUBDIR+=	higan
 SUBDIR+=	higgsbounds
 SUBDIR+=	hijra
@@ -5871,7 +5873,6 @@ SUBDIR+=	yersinia
 SUBDIR+=	yet-another-cloudwatch-exporter
 SUBDIR+=	yi
 SUBDIR+=	yoda
-SUBDIR+=	yosys
 SUBDIR+=	you-get
 SUBDIR+=	yp-tools
 SUBDIR+=	ypbind-mt
diff --git a/yosys/DESCR b/yosys/DESCR
deleted file mode 100644
index 734d4f6748..0000000000
--- a/yosys/DESCR
+++ /dev/null
@@ -1,2 +0,0 @@
-Yosys currently has extensive Verilog-2005 support and provides a basic set of
-synthesis algorithms for various application domains.
diff --git a/yosys/Makefile b/yosys/Makefile
deleted file mode 100644
index 7b89d61ea5..0000000000
--- a/yosys/Makefile
+++ /dev/null
@@ -1,83 +0,0 @@
-# $NetBSD$
-
-GITHUB_PROJECT=	yosys
-GITHUB_TAG=	refs/tags/${DISTNAME}
-DISTNAME=	yosys-0.33
-CATEGORIES=	devel
-MASTER_SITES=	${MASTER_SITE_GITHUB:=YosysHQ/}
-
-MAINTAINER=	pkgsrc-users%NetBSD.org@localhost
-HOMEPAGE=	https://yosyshq.net/yosys/
-COMMENT=	Framework for Verilog RTL synthesis
-LICENSE=	isc
-
-USE_LANGUAGES+=			c c++
-USE_TOOLS+=			gmake pkg-config bison gawk flex bash:test
-PYTHON_VERSIONS_INCOMPATIBLE=	27
-
-WRKSRC=			${WRKDIR}/yosys-${DISTNAME}
-TEST_TARGET=		test
-
-REPLACE_SH+=		tests/svinterfaces/runone.sh
-REPLACE_SH+=		tests/svinterfaces/run_simple.sh
-
-SUBST_CLASSES+=		python3
-SUBST_MESSAGE.python3=	Fixing non-shellbang references to python3.
-SUBST_STAGE.python3=	pre-configure
-SUBST_SED.python3=	-e 's,python3,${PYTHONBIN},g'
-SUBST_FILES.python3+=	Makefile
-SUBST_FILES.python3+=	tests/bram/run-test.sh
-SUBST_FILES.python3+=	tests/fsm/run-test.sh
-SUBST_FILES.python3+=	tests/memlib/run-test.sh
-SUBST_FILES.python3+=	tests/opt_share/run-test.sh
-SUBST_FILES.python3+=	tests/realmath/run-test.sh
-SUBST_FILES.python3+=	tests/rpc/exec.ys
-SUBST_FILES.python3+=	tests/rpc/run-test.sh
-SUBST_FILES.python3+=	tests/share/run-test.sh
-SUBST_FILES.python3+=	tests/xprop/run-test.sh
-SUBST_FILES.python3+=	tests/xprop/generate.py
-
-SUBST_CLASSES+=		python
-SUBST_MESSAGE.python=	Fixing shellbang references to python3.
-SUBST_STAGE.python=	pre-configure
-SUBST_SED.python=	-e 's,/usr/bin/env python3,${PYTHONBIN},g'
-SUBST_FILES.python=	backends/edif/runtest.py
-SUBST_FILES.python+=	backends/smt2/smtbmc.py
-SUBST_FILES.python+=	passes/pmgen/pmgen.py
-SUBST_FILES.python+=	techlibs/common/cellhelp.py
-SUBST_FILES.python+=	techlibs/nexus/cells_xtra.py
-SUBST_FILES.python+=	techlibs/xilinx/cells_xtra.py
-SUBST_FILES.python+=	tests/bram/generate.py
-SUBST_FILES.python+=	tests/fsm/generate.py
-SUBST_FILES.python+=	tests/opt_share/generate.py
-SUBST_FILES.python+=	tests/realmath/generate.py
-SUBST_FILES.python+=	tests/share/generate.py
-SUBST_FILES.python+=	tests/tools/txt2tikztiming.py
-
-.include "../../mk/bsd.prefs.mk"
-
-.if ${OPSYS} != "Linux"
-BUILDLINK_TRANSFORM=	rm:-ldl
-.endif
-
-do-configure:
-	${RUN} ${ECHO} 'CONFIG := ${YOSYS_CONFIG}' > ${WRKSRC}/Makefile.conf
-
-# pkgsrc verilog isn't new enough
-#TEST_DEPENDS+=		iverilog-[0-9]*:../../cad/iverilog
-
-.include "../../lang/python/pyversion.mk"
-.include "../../lang/tcl/buildlink3.mk"
-.include "../../devel/readline/buildlink3.mk"
-.include "../../lang/python/application.mk"
-.include "../../devel/libffi/buildlink3.mk"
-.include "../../mk/bsd.pkg.mk"
-
-.if !empty(PKGSRC_COMPILER:Mclang)
-YOSYS_CONFIG=		clang
-.elif !empty(PKGSRC_COMPILER:Mgcc)
-YOSYS_CONFIG=		gcc
-GCC_REQD+=		4.8.1
-.else
-.  error Yosys must be compiled with either GCC or Clang
-.endif
diff --git a/yosys/PLIST b/yosys/PLIST
deleted file mode 100644
index ef16090154..0000000000
--- a/yosys/PLIST
+++ /dev/null
@@ -1,262 +0,0 @@
-@comment $NetBSD$
-bin/yosys
-bin/yosys-abc
-bin/yosys-config
-bin/yosys-filterlib
-bin/yosys-smtbmc
-bin/yosys-witness
-share/yosys/abc9_map.v
-share/yosys/abc9_model.v
-share/yosys/abc9_unmap.v
-share/yosys/achronix/speedster22i/cells_map.v
-share/yosys/achronix/speedster22i/cells_sim.v
-share/yosys/adff2dff.v
-share/yosys/anlogic/arith_map.v
-share/yosys/anlogic/brams.txt
-share/yosys/anlogic/brams_map.v
-share/yosys/anlogic/cells_map.v
-share/yosys/anlogic/cells_sim.v
-share/yosys/anlogic/eagle_bb.v
-share/yosys/anlogic/lutrams.txt
-share/yosys/anlogic/lutrams_map.v
-share/yosys/cells.lib
-share/yosys/cmp2lcu.v
-share/yosys/cmp2lut.v
-share/yosys/coolrunner2/cells_counter_map.v
-share/yosys/coolrunner2/cells_latch.v
-share/yosys/coolrunner2/cells_sim.v
-share/yosys/coolrunner2/tff_extract.v
-share/yosys/coolrunner2/xc2_dff.lib
-share/yosys/dff2ff.v
-share/yosys/ecp5/arith_map.v
-share/yosys/ecp5/brams.txt
-share/yosys/ecp5/brams_map.v
-share/yosys/ecp5/cells_bb.v
-share/yosys/ecp5/cells_ff.vh
-share/yosys/ecp5/cells_io.vh
-share/yosys/ecp5/cells_map.v
-share/yosys/ecp5/cells_sim.v
-share/yosys/ecp5/dsp_map.v
-share/yosys/ecp5/latches_map.v
-share/yosys/ecp5/lutrams.txt
-share/yosys/ecp5/lutrams_map.v
-share/yosys/efinix/arith_map.v
-share/yosys/efinix/brams.txt
-share/yosys/efinix/brams_map.v
-share/yosys/efinix/cells_map.v
-share/yosys/efinix/cells_sim.v
-share/yosys/efinix/gbuf_map.v
-share/yosys/fabulous/arith_map.v
-share/yosys/fabulous/cells_map.v
-share/yosys/fabulous/ff_map.v
-share/yosys/fabulous/io_map.v
-share/yosys/fabulous/latches_map.v
-share/yosys/fabulous/prims.v
-share/yosys/fabulous/ram_regfile.txt
-share/yosys/fabulous/regfile_map.v
-share/yosys/gate2lut.v
-share/yosys/gatemate/arith_map.v
-share/yosys/gatemate/brams.txt
-share/yosys/gatemate/brams_init_20.vh
-share/yosys/gatemate/brams_init_40.vh
-share/yosys/gatemate/brams_map.v
-share/yosys/gatemate/cells_bb.v
-share/yosys/gatemate/cells_sim.v
-share/yosys/gatemate/inv_map.v
-share/yosys/gatemate/lut_map.v
-share/yosys/gatemate/lut_tree_cells.genlib
-share/yosys/gatemate/lut_tree_map.v
-share/yosys/gatemate/mul_map.v
-share/yosys/gatemate/mux_map.v
-share/yosys/gatemate/reg_map.v
-share/yosys/gowin/arith_map.v
-share/yosys/gowin/brams.txt
-share/yosys/gowin/brams_map.v
-share/yosys/gowin/cells_map.v
-share/yosys/gowin/cells_sim.v
-share/yosys/gowin/cells_xtra.v
-share/yosys/gowin/lutrams.txt
-share/yosys/gowin/lutrams_map.v
-share/yosys/greenpak4/cells_blackbox.v
-share/yosys/greenpak4/cells_latch.v
-share/yosys/greenpak4/cells_map.v
-share/yosys/greenpak4/cells_sim.v
-share/yosys/greenpak4/cells_sim_ams.v
-share/yosys/greenpak4/cells_sim_digital.v
-share/yosys/greenpak4/cells_sim_wip.v
-share/yosys/greenpak4/gp_dff.lib
-share/yosys/ice40/abc9_model.v
-share/yosys/ice40/arith_map.v
-share/yosys/ice40/brams.txt
-share/yosys/ice40/brams_map.v
-share/yosys/ice40/cells_map.v
-share/yosys/ice40/cells_sim.v
-share/yosys/ice40/dsp_map.v
-share/yosys/ice40/ff_map.v
-share/yosys/ice40/latches_map.v
-share/yosys/ice40/spram.txt
-share/yosys/ice40/spram_map.v
-share/yosys/include/backends/cxxrtl/cxxrtl.h
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_capi.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd.h
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
-share/yosys/include/backends/cxxrtl/cxxrtl_vcd_capi.h
-share/yosys/include/backends/rtlil/rtlil_backend.h
-share/yosys/include/frontends/ast/ast.h
-share/yosys/include/frontends/ast/ast_binding.h
-share/yosys/include/frontends/blif/blifparse.h
-share/yosys/include/kernel/binding.h
-share/yosys/include/kernel/cellaigs.h
-share/yosys/include/kernel/celledges.h
-share/yosys/include/kernel/celltypes.h
-share/yosys/include/kernel/consteval.h
-share/yosys/include/kernel/constids.inc
-share/yosys/include/kernel/ff.h
-share/yosys/include/kernel/ffinit.h
-share/yosys/include/kernel/fstdata.h
-share/yosys/include/kernel/hashlib.h
-share/yosys/include/kernel/json.h
-share/yosys/include/kernel/log.h
-share/yosys/include/kernel/macc.h
-share/yosys/include/kernel/mem.h
-share/yosys/include/kernel/modtools.h
-share/yosys/include/kernel/qcsat.h
-share/yosys/include/kernel/register.h
-share/yosys/include/kernel/rtlil.h
-share/yosys/include/kernel/satgen.h
-share/yosys/include/kernel/sigtools.h
-share/yosys/include/kernel/utils.h
-share/yosys/include/kernel/yosys.h
-share/yosys/include/kernel/yw.h
-share/yosys/include/libs/ezsat/ezminisat.h
-share/yosys/include/libs/ezsat/ezsat.h
-share/yosys/include/libs/fst/fstapi.h
-share/yosys/include/libs/json11/json11.hpp
-share/yosys/include/libs/sha1/sha1.h
-share/yosys/include/passes/fsm/fsmdata.h
-share/yosys/intel/common/altpll_bb.v
-share/yosys/intel/common/brams_m9k.txt
-share/yosys/intel/common/brams_map_m9k.v
-share/yosys/intel/common/ff_map.v
-share/yosys/intel/common/m9k_bb.v
-share/yosys/intel/cyclone10lp/cells_map.v
-share/yosys/intel/cyclone10lp/cells_sim.v
-share/yosys/intel/cycloneiv/cells_map.v
-share/yosys/intel/cycloneiv/cells_sim.v
-share/yosys/intel/cycloneive/cells_map.v
-share/yosys/intel/cycloneive/cells_sim.v
-share/yosys/intel/max10/cells_map.v
-share/yosys/intel/max10/cells_sim.v
-share/yosys/intel_alm/common/abc9_map.v
-share/yosys/intel_alm/common/abc9_model.v
-share/yosys/intel_alm/common/abc9_unmap.v
-share/yosys/intel_alm/common/alm_map.v
-share/yosys/intel_alm/common/alm_sim.v
-share/yosys/intel_alm/common/arith_alm_map.v
-share/yosys/intel_alm/common/bram_m10k.txt
-share/yosys/intel_alm/common/bram_m10k_map.v
-share/yosys/intel_alm/common/bram_m20k.txt
-share/yosys/intel_alm/common/bram_m20k_map.v
-share/yosys/intel_alm/common/dff_map.v
-share/yosys/intel_alm/common/dff_sim.v
-share/yosys/intel_alm/common/dsp_map.v
-share/yosys/intel_alm/common/dsp_sim.v
-share/yosys/intel_alm/common/lutram_mlab.txt
-share/yosys/intel_alm/common/megafunction_bb.v
-share/yosys/intel_alm/common/mem_sim.v
-share/yosys/intel_alm/common/misc_sim.v
-share/yosys/intel_alm/common/quartus_rename.v
-share/yosys/intel_alm/cyclonev/cells_sim.v
-share/yosys/lattice/arith_map_ccu2c.v
-share/yosys/lattice/arith_map_ccu2d.v
-share/yosys/lattice/brams_16kd.txt
-share/yosys/lattice/brams_8kc.txt
-share/yosys/lattice/brams_map_16kd.v
-share/yosys/lattice/brams_map_8kc.v
-share/yosys/lattice/ccu2c_sim.vh
-share/yosys/lattice/ccu2d_sim.vh
-share/yosys/lattice/cells_bb_ecp5.v
-share/yosys/lattice/cells_bb_xo2.v
-share/yosys/lattice/cells_bb_xo3.v
-share/yosys/lattice/cells_bb_xo3d.v
-share/yosys/lattice/cells_ff.vh
-share/yosys/lattice/cells_io.vh
-share/yosys/lattice/common_sim.vh
-share/yosys/lattice/dsp_map_18x18.v
-share/yosys/lattice/latches_map.v
-share/yosys/lattice/cells_map.v
-share/yosys/lattice/cells_sim_ecp5.v
-share/yosys/lattice/cells_sim_xo2.v
-share/yosys/lattice/cells_sim_xo3.v
-share/yosys/lattice/cells_sim_xo3d.v
-share/yosys/lattice/lutrams.txt
-share/yosys/lattice/lutrams_map.v
-share/yosys/mul2dsp.v
-share/yosys/nexus/arith_map.v
-share/yosys/nexus/brams.txt
-share/yosys/nexus/brams_map.v
-share/yosys/nexus/cells_map.v
-share/yosys/nexus/cells_sim.v
-share/yosys/nexus/cells_xtra.v
-share/yosys/nexus/dsp_map.v
-share/yosys/nexus/latches_map.v
-share/yosys/nexus/lrams.txt
-share/yosys/nexus/lrams_map.v
-share/yosys/nexus/lutrams.txt
-share/yosys/nexus/lutrams_map.v
-share/yosys/nexus/parse_init.vh
-share/yosys/pmux2mux.v
-share/yosys/python3/smtio.py
-share/yosys/python3/ywio.py
-share/yosys/quicklogic/abc9_map.v
-share/yosys/quicklogic/abc9_model.v
-share/yosys/quicklogic/abc9_unmap.v
-share/yosys/quicklogic/cells_sim.v
-share/yosys/quicklogic/lut_sim.v
-share/yosys/quicklogic/pp3_cells_map.v
-share/yosys/quicklogic/pp3_cells_sim.v
-share/yosys/quicklogic/pp3_ffs_map.v
-share/yosys/quicklogic/pp3_latches_map.v
-share/yosys/quicklogic/pp3_lut_map.v
-share/yosys/sf2/arith_map.v
-share/yosys/sf2/cells_map.v
-share/yosys/sf2/cells_sim.v
-share/yosys/simcells.v
-share/yosys/simlib.v
-share/yosys/smtmap.v
-share/yosys/techmap.v
-share/yosys/xilinx/abc9_model.v
-share/yosys/xilinx/arith_map.v
-share/yosys/xilinx/brams_defs.vh
-share/yosys/xilinx/brams_xc2v.txt
-share/yosys/xilinx/brams_xc2v_map.v
-share/yosys/xilinx/brams_xc3sda.txt
-share/yosys/xilinx/brams_xc3sda_map.v
-share/yosys/xilinx/brams_xc4v.txt
-share/yosys/xilinx/brams_xc4v_map.v
-share/yosys/xilinx/brams_xc5v_map.v
-share/yosys/xilinx/brams_xc6v_map.v
-share/yosys/xilinx/brams_xcu_map.v
-share/yosys/xilinx/brams_xcv.txt
-share/yosys/xilinx/brams_xcv_map.v
-share/yosys/xilinx/cells_map.v
-share/yosys/xilinx/cells_sim.v
-share/yosys/xilinx/cells_xtra.v
-share/yosys/xilinx/ff_map.v
-share/yosys/xilinx/lut_map.v
-share/yosys/xilinx/lutrams_xc5v.txt
-share/yosys/xilinx/lutrams_xc5v_map.v
-share/yosys/xilinx/lutrams_xcu.txt
-share/yosys/xilinx/lutrams_xcv.txt
-share/yosys/xilinx/lutrams_xcv_map.v
-share/yosys/xilinx/mux_map.v
-share/yosys/xilinx/urams.txt
-share/yosys/xilinx/urams_map.v
-share/yosys/xilinx/xc3s_mult_map.v
-share/yosys/xilinx/xc3sda_dsp_map.v
-share/yosys/xilinx/xc4v_dsp_map.v
-share/yosys/xilinx/xc5v_dsp_map.v
-share/yosys/xilinx/xc6s_dsp_map.v
-share/yosys/xilinx/xc7_dsp_map.v
-share/yosys/xilinx/xcu_dsp_map.v
diff --git a/yosys/distinfo b/yosys/distinfo
deleted file mode 100644
index 4a96edab5d..0000000000
--- a/yosys/distinfo
+++ /dev/null
@@ -1,6 +0,0 @@
-$NetBSD$
-
-BLAKE2s (yosys-0.33.tar.gz) = 77600fe6839b7ffa2c8655b1b3290bb595e09d63a9b67ee7791d5d8bbdbbde28
-SHA512 (yosys-0.33.tar.gz) = e635df2b5fccf14a45c2f8ec342e7415105a46383333f11b7509907f197adc74a04b7fbb56eadddbb68dc5671619770892a0a93210ba68ef23044bf52d70f616
-Size (yosys-0.33.tar.gz) = 2586120 bytes
-SHA1 (patch-kernel_yosys.cc) = 81e504f0a61baa47eca7cec021ae60d8ed432e3b
diff --git a/yosys/patches/patch-kernel_yosys.cc b/yosys/patches/patch-kernel_yosys.cc
deleted file mode 100644
index 0433af4440..0000000000
--- a/yosys/patches/patch-kernel_yosys.cc
+++ /dev/null
@@ -1,38 +0,0 @@
-$NetBSD$
-
-support NetBSD
-
---- kernel/yosys.cc.orig	2021-11-01 14:44:53.161071165 +0000
-+++ kernel/yosys.cc
-@@ -55,7 +55,7 @@
- #  include <glob.h>
- #endif
- 
--#ifdef __FreeBSD__
-+#if defined(__FreeBSD__) || defined(__NetBSD__)
- #  include <sys/sysctl.h>
- #endif
- 
-@@ -790,6 +790,22 @@ std::string proc_self_dirname()
- 	free(buffer);
- 	return path;
- }
-+#elif defined(__NetBSD__)
-+std::string proc_self_dirname()
-+{
-+	const int mib[4] = {CTL_KERN, KERN_PROC_ARGS, -1, KERN_PROC_PATHNAME};
-+	char *buffer;
-+	size_t buflen;
-+	std::string path;
-+	buffer = (char *)asysctl(mib, 4, &buflen);
-+	if (buffer == NULL)
-+		log_error("sysctl failed: %s\n", strerror(errno));
-+	while (buflen > 0 && buffer[buflen-1] != '/')
-+		buflen--;
-+	path.assign(buffer, buflen);
-+	free(buffer);
-+	return path;
-+}
- #elif defined(__APPLE__)
- std::string proc_self_dirname()
- {
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