(cad/iverilog) Candidate for updating 12.0

To: pkgsrc-wip-changes%NetBSD.org@localhost
Subject: (cad/iverilog) Candidate for updating 12.0
From: Makoto mef Fujiwara <makoto%ki.nu@localhost>
Date: Sat, 18 May 2024 15:24:40 +0000
Module Name:	pkgsrc-wip
Committed By:	Makoto mef Fujiwara <makoto%ki.nu@localhost>
Pushed By:	mef
Date:		Sun May 19 00:22:23 2024 +0900
Changeset:	1e6a7c07f5ce5ad818697867775c5383672f51c8

Added Files:
	iverilog/DESCR
	iverilog/Makefile
	iverilog/PLIST
	iverilog/TODO
	iverilog/buildlink3.mk
	iverilog/distinfo
	iverilog/patches/patch-aa
	iverilog/patches/patch-cadpli_Makefile.in

Log Message:
(cad/iverilog) Candidate for updating 12.0

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=1e6a7c07f5ce5ad818697867775c5383672f51c8

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 iverilog/DESCR                            |  6 ++++
 iverilog/Makefile                         | 37 +++++++++++++++++++++
 iverilog/PLIST                            | 54 +++++++++++++++++++++++++++++++
 iverilog/TODO                             |  1 +
 iverilog/buildlink3.mk                    | 16 +++++++++
 iverilog/distinfo                         | 11 +++++++
 iverilog/patches/patch-aa                 | 14 ++++++++
 iverilog/patches/patch-cadpli_Makefile.in | 17 ++++++++++
 8 files changed, 156 insertions(+)

diffs:
diff --git a/iverilog/DESCR b/iverilog/DESCR
new file mode 100644
index 0000000000..6e1388e279
--- /dev/null
+++ b/iverilog/DESCR
@@ -0,0 +1,6 @@
+Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
+the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
+handle a mix of structural and behavioral constructs.
+
+Icarus Verilog is not aimed at being a simulator in the traditional sense, but
+a compiler that generates code employed by back-end tools.
diff --git a/iverilog/Makefile b/iverilog/Makefile
new file mode 100644
index 0000000000..32d93eb668
--- /dev/null
+++ b/iverilog/Makefile
@@ -0,0 +1,37 @@
+# $NetBSD: Makefile,v 1.3 2024/05/18 14:49:59 mef Exp $
+
+DISTNAME=	verilog-12.0
+# There is confision in naming of this software, use iverilog as it's saner
+PKGNAME=	i${DISTNAME}
+CATEGORIES=	cad
+MASTER_SITES=	${MASTER_SITE_GITHUB:=steveicarus/}
+GITHUB_TAG=	v${PKGVERSION_NOREV:S/./_/}
+
+MAINTAINER=	dmcmahill%NetBSD.org@localhost
+HOMEPAGE=	https://steveicarus.github.io/iverilog/
+COMMENT=	Verilog simulation and synthesis tool (stable release version)
+LICENSE=	gnu-gpl-v2
+
+USE_LANGUAGES=	c c++
+#RKSRC=		${WRKDIR}/${PKGNAME_NOREV}
+
+GNU_CONFIGURE=		yes
+USE_TOOLS+=		gmake bison lex autoconf
+TEST_TARGET=		check
+
+INSTALLATION_DIRS+=	share/doc/ivl
+
+pre-configure:
+	(cd ${WRKSRC}; autoconf)
+# Additional files
+post-install:
+	cd ${WRKSRC}; ${INSTALL_DATA} \
+		QUICK_START.txt \
+		README.md      \
+	${DESTDIR}${PREFIX}/share/doc/ivl
+
+.include "../../devel/gperf/buildlink3.mk"
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../archivers/bzip2/buildlink3.mk"
+.include "../../mk/readline.buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/iverilog/PLIST b/iverilog/PLIST
new file mode 100644
index 0000000000..b8d196c28a
--- /dev/null
+++ b/iverilog/PLIST
@@ -0,0 +1,54 @@
+@comment $NetBSD$
+bin/iverilog
+bin/iverilog-vpi
+bin/vvp
+include/iverilog/_pli_types.h
+include/iverilog/acc_user.h
+include/iverilog/ivl_target.h
+include/iverilog/sv_vpi_user.h
+include/iverilog/veriuser.h
+include/iverilog/vpi_user.h
+lib/ivl/blif-s.conf
+lib/ivl/blif.conf
+lib/ivl/blif.tgt
+lib/ivl/cadpli.vpl
+lib/ivl/include/constants.vams
+lib/ivl/include/disciplines.vams
+lib/ivl/ivl
+lib/ivl/ivlpp
+lib/ivl/null-s.conf
+lib/ivl/null.conf
+lib/ivl/null.tgt
+lib/ivl/pcb-s.conf
+lib/ivl/pcb.conf
+lib/ivl/pcb.tgt
+lib/ivl/sizer-s.conf
+lib/ivl/sizer.conf
+lib/ivl/sizer.tgt
+lib/ivl/stub-s.conf
+lib/ivl/stub.conf
+lib/ivl/stub.tgt
+lib/ivl/system.vpi
+lib/ivl/v2005_math.vpi
+lib/ivl/v2009.vpi
+lib/ivl/va_math.vpi
+lib/ivl/vhdl-s.conf
+lib/ivl/vhdl.conf
+lib/ivl/vhdl.tgt
+lib/ivl/vhdl_sys.vpi
+lib/ivl/vhdl_textio.vpi
+lib/ivl/vhdlpp
+lib/ivl/vlog95-s.conf
+lib/ivl/vlog95.conf
+lib/ivl/vlog95.tgt
+lib/ivl/vpi_debug.vpi
+lib/ivl/vvp-s.conf
+lib/ivl/vvp.conf
+lib/ivl/vvp.tgt
+lib/libveriuser.a
+lib/libvpi.a
+man/man1/iverilog-vpi.1
+man/man1/iverilog.1
+man/man1/vvp.1
+share/doc/ivl/QUICK_START.txt
+share/doc/ivl/README.md
diff --git a/iverilog/TODO b/iverilog/TODO
new file mode 100644
index 0000000000..b209ab28d3
--- /dev/null
+++ b/iverilog/TODO
@@ -0,0 +1 @@
+- Find ChangeLog
diff --git a/iverilog/buildlink3.mk b/iverilog/buildlink3.mk
new file mode 100644
index 0000000000..e9cb1d61d2
--- /dev/null
+++ b/iverilog/buildlink3.mk
@@ -0,0 +1,16 @@
+# $NetBSD: buildlink3.mk,v 1.2 2018/01/07 13:03:56 rillig Exp $
+
+BUILDLINK_TREE+=	iverilog
+
+.if !defined(IVERILOG_BUILDLINK3_MK)
+IVERILOG_BUILDLINK3_MK:=
+
+BUILDLINK_API_DEPENDS.iverilog+=	iverilog>=10.1.1
+BUILDLINK_PKGSRCDIR.iverilog?=		../../cad/iverilog
+
+.include "../../devel/gperf/buildlink3.mk"
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../archivers/bzip2/buildlink3.mk"
+.endif	# IVERILOG_BUILDLINK3_MK
+
+BUILDLINK_TREE+=	-iverilog
diff --git a/iverilog/distinfo b/iverilog/distinfo
new file mode 100644
index 0000000000..7bd566c069
--- /dev/null
+++ b/iverilog/distinfo
@@ -0,0 +1,11 @@
+$NetBSD: distinfo,v 1.7 2021/10/26 10:04:12 nia Exp $
+
+BLAKE2s (verilog-12.0.tar.gz) = a33ac3b9c33cc7600355da36a64b82411d00eb26c385b717052a0817aa1ee22b
+SHA512 (verilog-12.0.tar.gz) = a8e112f760903335ef2fbf00529e5fe282b83c1f583c4316373b9410d7fad2a53d5c4adb82dd62491c14a620cb5b1fab117cb0cde638c86b65fe5b7b0dd07152
+Size (verilog-12.0.tar.gz) = 2995096 bytes
+SHA1 (patch-Makefile.in) = 9e66fedfa8487be3b7f82c152504404545f8bd06
+SHA1 (patch-aa) = cf075110416f6db0892129796cd83b8ae8de55fa
+SHA1 (patch-cadpli_Makefile.in) = ed21a5f529ac449c26b831cbd5fde052d9ed5466
+SHA1 (patch-tgt-pcb_Makefile.in) = 0ea212a678aabd7e3d131322fd1a867b3e22611f
+SHA1 (patch-vhdlpp_Makefile.in) = feed15f8e8e60c73b0f1f25a62d30fec7fa25a01
+SHA1 (patch-vvp_Makefile.in) = 67bef8f6bbf03c8cf548785f5d8124e03771026a
diff --git a/iverilog/patches/patch-aa b/iverilog/patches/patch-aa
new file mode 100644
index 0000000000..0c5a42d550
--- /dev/null
+++ b/iverilog/patches/patch-aa
@@ -0,0 +1,14 @@
+$NetBSD: patch-aa,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+gcc44 fixes
+
+--- elab_net.cc.orig	2010-09-27 17:42:32.000000000 +0000
++++ elab_net.cc
+@@ -26,6 +26,7 @@
+ 
+ # include  <cstdlib>
+ # include  <cstring>
++# include  <memory>
+ # include  <iostream>
+ # include  "ivl_assert.h"
+ 
diff --git a/iverilog/patches/patch-cadpli_Makefile.in b/iverilog/patches/patch-cadpli_Makefile.in
new file mode 100644
index 0000000000..75fb57eda8
--- /dev/null
+++ b/iverilog/patches/patch-cadpli_Makefile.in
@@ -0,0 +1,17 @@
+$NetBSD: patch-cadpli_Makefile.in,v 1.1 2020/03/26 02:37:14 joerg Exp $
+
+gcc -std=gnu99 -shared -L/usr/lib -Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib -o cadpli.vpl cadpli.o ../libveriuser/libveriuser.o -L../vvp -lvpi
+mkdir: dep: Not a directory
+Makefile:52: recipe for target 'dep' failed
+
+--- cadpli/Makefile.in~	2013-08-20 04:10:31.000000000 +0900
++++ cadpli/Makefile.in	2013-12-20 22:03:29.000000000 +0900
+@@ -51,7 +51,7 @@ check: all
+ dep:
+ 	mkdir dep
+ 
+-%.o: %.c
++%.o: %.c dep
+ 	$(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
+ 	mv $*.d dep
+
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