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CVS commit: wip/mvsis
Module name: wip
Committed by: dhowland
Date: Wed Nov 15 17:51:47 UTC 2006
Import into wip/mvsis
Log Message:
The MVSIS group at Berkeley studies logic synthesis and verification for VLSI
design. The main focus is on new optimization algorithms that improve the
quality of circuits generated by automatic synthesis tools and, at the same
time, are scalable for practical use.
Status:
Vendor Tag: dhowland
Release Tags: dhowland_20061114
N wip/mvsis/PLIST
N wip/mvsis/Makefile
N wip/mvsis/DESCR
N wip/mvsis/distinfo
No conflicts created by this import
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