On Wed, 11 Aug 1999 19:39:55 -0500 
 seebs@plethora.net (Peter Seebach) wrote:

I won't bother with the IDE question, as that has already been answered
thoroughly enough :-)

 > BTW, I'm a bit confused by the alpha environment - do I run out of interrupts
 > on an alpha the way I do on a PC?  I notice that IRQ's I've never seen
 > available on a PC seem to be showing up - for instance, my ethernet is on irq
 > 2.

...thor's answer here was only partially right.  Yes, PCI interrupts are
sharable, because they're all level-triggered.  However, the Alpha is
even cooler than that.

On the PC (and on some older Alpha models, specifically 21064+APECS and
some LCA models), PCI interrupts are routed through the ISA PIC(s).  These
interrupt controllers have 8 interrupt lines each.  There are two such
controllers, and you end up with 15 interrupt lines (I think :-) after all
is said and done.

On more modern Alphas, like the PC164, ISA and PCI interrupts are handled
separately.  ISA interrupts, via the ISA PIC, come in on one set of vectors,
while PCI interrupts come in on a completely separate set.  PCI interrupts
also live in a completely separate "IRQ space", which is why you see things
like:

foo0: interrupting at eb164 irq 18
...
bar0: interrupt at isa irq 5

An "isa irq" is not the same thing as an "eb164 irq" :-)

There are also typically enough PCI interrupt vectors for the entire
range of device/line/pin combinations on the root PCI bus, so sharing
isn't ususally necessary (the exception being when PCI-PCI bridges
are thrown in the mix).

Basically, the Alpha's interrupt scheme (apart from the fact that
there's a different routing scheme for each model, grumble) doesn't
suck.

Hope that clarifies things a little.

        -- Jason R. Thorpe <thorpej@nas.nasa.gov>