In message <19990813130609.A7406@rek.tjls.com>, Thor Lancelot Simon writes:
>On Fri, Aug 13, 1999 at 10:55:15AM -0400, Michael T. Stolarchuk wrote:
>>       Fast back-to-back transactions: off
>
>This may disable bursting.  I haven't got the mindshare book or PCI
>standard to check, though.
>
>>     Latency Timer: 0x00
>
>This is wrong.  Try putting 0x20 in there _on every device in the machine_.
>
>>     Cache Line Size: 0x00
>
>I *think* this is wrong, too.  I think it should be set to 0x40 (again,
>everywhere).
>

hmm.  i'm having trouble verifying that the cache line size is getting
set correctly...  here's the code in pci.c that i'm using:


                        /* config_found_sm(self, &pa, pciprint, pcisubmatch); */
                        if ((d = config_found_sm(self, &pa, pciprint, pcisubmatch))) {
                                u_int32_t v;
                                v = pci_conf_read(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG);
                                printf ("%s: Changing (%x) pci latency from %d to %d\n",
                                        d->dv_xname, v, (v & PCI_LATTIMER_MASK) >>
                                        PCI_LATTIMER_SHIFT, PCI_FORCE_LATENCY);
                                v &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
                                v |= PCI_FORCE_LATENCY << PCI_LATTIMER_SHIFT;
                                v &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
                                v |= 0x40 << PCI_CACHELINE_SHIFT;
                                printf ("%s: Changing pci value %x\n",
                                        d->dv_xname, v );
                                pci_conf_write(pa.pa_pc, pa.pa_tag, PCI_BHLC_REG, v);
                                pci_conf_print( pa.pa_pc, pa.pa_tag, NULL );
                        }

here's the result:

pciide0: Changing (2000) pci latency from 0 to 32
pciide0: Changing pci value 2040
PCI configuration registers:
  Common header:
    0x00: 0x06461095 0x02800005 0x01018001 0x00002000

    Vendor Name: CMD Technology (0x1095)
    Device Name: PCI0646 (0x0646)
    Command register: 0x0005
      I/O space accesses: on
      Memory space accesses: off
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
    Status register: 0x0280
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: mass storage (0x01)
    Subclass Name: IDE (0x01)
    Interface: 0x80
    Revision ID: 0x01
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x20
    Cache Line Size: 0x00

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00010191 0x00000000 0x00000000 0x00000000
    0x30: 0x00000000 0x00000000 0x00000000 0x04020105

What have i done wrong?

mts.