On Sun, 5 Dec 1999 02:08:43 -0500 (EST) 
 der Mouse <mouse@Rodents.Montreal.QC.CA> wrote:

 > The problem is with the implementation: when you can't *get* "their TLB
 > reloading code", you don't have enough info to write your own. :-(

Okay, to nit-pick... :-)

For the processor-specific bits, this is "easy"; all of the processor
manuals are available.  So, I could write my own TLB reloading code
if I felt so inclined :-)

The "hard" part is the model-specific bits.  This means that I can't
write my own interrupt routing code, etc.  All the stuff that differs
between models (even models with the same core logic).

There's an amusing story related to this... basically, since interrupts
were just about the *only* thing not specified in the architecture,
apparently rivalry between groups within DEC (i.e. the groups working
on the individual systems) resulted in the proliferation of different
interrupt schemes we see today on the various systypes.

I mean, really.. Look at the AlphaServer 1000 vs. 1000A.  They differ
by, like, the interrupt controller they use.  How funny is that?!  :-)

        -- Jason R. Thorpe <thorpej@nas.nasa.gov>