On Wed, Feb 16, 2000 at 09:38:18PM -0500, Allen Briggs wrote:
> was there.  I double-checked and triple-checked the asm code for the
> lock, and it looked awfully correct.  See my message(s) in the archive
> from a couple months back with the subject "Some assembly required" or
> some such.

I remember the thread. It wasn't relevant to me at the time since my
semester hadn't started yet so I wasn't in my dippy "e-commerce" class yet.
It's a senior-level Comp.Sci class, too. *shakes head* 

Anyway....

Say, is a memory barrier instruction needed after unlocking a lock?
Currently unlocking is done by a memory barrier followed by
"*(lock) = 0;".

Here's something else:

(I)5-22 in 5.6.3 Implied Barriers says "There are no implied barriers in
Alpha". 

Then on the next page it says, for a "Single Processor Data Stream",
that "No barriers are ever needed. A read to physical address X will
always return the value written by the immediately preceding write to
X in the processor issue sequence.". 

Now, the question:

Does that include the lock locked and store conditional instructions? Always?


I'm currently doing a build with FLAGS:
"-g -DLOCKDEBUG -DLOCK_MGR_DEBUG -DDEADLOCK_DEBUG -save-temps"
-- 
Kevin P. Neal                                http://www.pobox.com/~kpn/

"In feeling small you gain the info you need."
     Ross Smith, on humility                        Apr 22 1999 2:22am