Re: timecounter TSC on Core i7

[Joerg Sonnenberger <joerg%britannica.bec.de@localhost>]

On Tue, Sep 15, 2009 at 01:26:13PM -0700, Paul Goyette wrote:
> On Tue, 15 Sep 2009, Joerg Sonnenberger wrote:
> 
> >On Tue, Sep 15, 2009 at 11:27:32AM -0700, Paul Goyette wrote:
> >>Would hpet be a better choice for timecounter?
> >
> >Not really. It is an order of magnitude slower. The best approach would
> >be to port the TSC sync code to the lapic timer, which is known to be
> >fixed frequency and also phase coherent, I think.
> 
> Hmm, I'm not even sure what a lapic is, or if/how it differs from
> the ioapic mentioned in my dmesg!  :)

The IO-APIC(s) obtain(s) interrupts from device and forwards them to the
local APIC bus. The L-APIC is part of the CPU/core and responsible for
notifying the CPU of interupt requests from the IO-APIC or other
L-APICs. The L-APIC has a local, per-core time interrupt and can also be
used as time counter.

Joerg