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Re: Areca 1200 rev. B not recognised?
> On Jul 4, 2019, at 1:42 PM, Lars-Johan Liman <liman%cafax.se@localhost> wrote:
>
> For the benefit of future people trawling this mailing list for this
> problem:
>
> Further digging has brought me to the conclusion that the ARECA 1200 and
> the ARECA 1200_B boards actually have different chip sets (hard as it is
> to believe ...). Looking at the array called "arc_devices[]" in arc.c from
> here:
>
> http://www.areca.us/support/s_freebsd/driver/openbsd_V1.20.0.0_121115/arc.c
>
> makes it quite obvious.
The fact that it's in the same driver implies that this won't be very hard at all. Although it looks to me like the OpenBSD driver doesn't actually support the 1200 rev B, because it call it a "type B" controller, but then fails to have any code to handle "type B" controllers in the places where different controller types need different handling.
>
> Well, well ... I'll see if I can find some "copious spare time" to use
> for an attempt to port the necessary code. Don't hold your breath,
> though ... Oh, and I'm not a kernel hacker to begin with. :-/
>
> Cheers,
> /Liman
>
> liman%cafax.se@localhost:
>> Continuing my own investigation.
>
>> liman%cafax.se@localhost:
>>> Is there an obvious reason for this being the case? What am I missing?
>>> ... ... SuperMicro stupidities?
>
>> It strikes me that the arcmsr0 is the only thing that interrupts at
>> ioapic1 (one) where everything else interrupts at ioapic0 (zero).
>
>> ; (keep-lines "ioapic" nil nil t)
>
>>> ioapic0 at mainbus0 apid 6: pa 0xfec00000, version 0x20, 24 pins
>>> ioapic1 at mainbus0 apid 7: pa 0xfec8a000, version 0x20, 24 pins
>>> arcmsr0: interrupting at ioapic1 pin 8
>>> uhci0: interrupting at ioapic0 pin 16
>>> uhci1: interrupting at ioapic0 pin 21
>>> uhci2: interrupting at ioapic0 pin 19
>>> ehci0: interrupting at ioapic0 pin 18
>>> uhci3: interrupting at ioapic0 pin 23
>>> uhci4: interrupting at ioapic0 pin 19
>>> uhci5: interrupting at ioapic0 pin 18
>>> ehci1: interrupting at ioapic0 pin 23
>>> piixide0: using ioapic0 pin 19 for native-PCI interrupt
>>> ichsmb0: interrupting at ioapic0 pin 18
>>> piixide1: using ioapic0 pin 19 for native-PCI interrupt
>
>> This could be related to the fact that the Areca board sits on a riser
>> card, with a sturdy IC (its heatsink covers its markings) on it. I
>> wonder if that riser card is the culprit. The lack of room prevents me
>> from mounting it directly on the MB, so I guess I will have to be
>> inventive somehow ... :-(
>
>> <goes back to the workshop with a frown ...> ;-)
>
>> Cheers,
>> /Liman
-- thorpej
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