Re: ahcisata clearing WDCTL_RST failed

[Manuel Bouyer <bouyer%antioche.eu.org@localhost>]

On Thu, Jul 04, 2019 at 10:56:56PM +0200, Jean-Yves Moulin wrote:
> 
> 
> > On 3 Jul 2019, at 23:37, Manuel Bouyer <bouyer%antioche.eu.org@localhost> wrote:
> >> I saw that there is some quirk in ahcisata_pci.c. But what should I change (I can provide PCI id for my controller) ?
> > 
> > Could you try pulling up ahcisata_core.c 1.75 and see if it helps ?
> 
> 
> I didn?t know how to pull one file only, so I built a current kernel (8.99.50).
> 
> Disk shown in hw.disknames, but fdisk cannot read it:
> 
> # fdisk: /dev/rwd0 is not a character device
> 
> 
> And dmesg says:
> 
> ahcisata0 port 0: device present, speed: 6.0Gb/s
> autoconfiguration error: ahcisata0 port 0: clearing WDCTL_RST failed for drive 15
> autoconfiguration error: ahcisata0 port 0: drive 15 reset failed, disabling PMP
> [?]
> ahcisata0 port 0: device present, speed: 6.0Gb/s
> wd0 ata atabus0 drive 0
> autoconfiguration error: ahcisata0 port 0: clearing WDCTL_RST failed for drive 0
> wd0: auto configuration error: IDENTIFY failed
> wd0: fixing 0 sector size
> wd0: secperunit and cylinders are zero
> wd0(ahcisata0:0:0): using PIO mode 0
> 
> 
> The WDCTL_RST error is printed twice for same drive, and this drive is called ?drive 15? then ?drive 0?.

"drive 15" is the SATA port multiplier address actually. It tries to
reset this port to see if there is a PMP present.

So disabling PMP support is not enough it seems.
Can you see if the attached patch against current helps ?

-- 
Manuel Bouyer <bouyer%antioche.eu.org@localhost>
     NetBSD: 26 ans d'experience feront toujours la difference
--

Index: ahcisata_core.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/ahcisata_core.c,v
retrieving revision 1.75
diff -u -p -u -r1.75 ahcisata_core.c
--- ahcisata_core.c	7 Apr 2019 17:46:49 -0000	1.75
+++ ahcisata_core.c	5 Jul 2019 07:01:32 -0000
@@ -1582,9 +1582,27 @@ ahci_channel_stop(struct ahci_softc *sc,
 		/* XXX controller reset ? */
 		return;
 	}
-
 	if (sc->sc_channel_stop)
 		sc->sc_channel_stop(sc, chp);
+	if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_FRE) == 0)
+		return;
+
+	AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel),
+	    AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_FRE);
+	/* wait 1s for FIS receive to stop */
+	for (i = 0; i <100; i++) {
+		if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_FR)
+		    == 0)
+			break;
+		if (flags & AT_WAIT)
+			tsleep(&sc, PRIBIO, "ahcistop", mstohz(10));
+		else
+			delay(10000);
+	}
+	if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_FR) {
+		printf("%s: channel FIS receive wouldn't stop\n", AHCINAME(sc));
+		/* XXX controller reset ? */
+	}
 }
 
 static void