Re: amigappc test kernel for CSPPC and BPPC

[Jukka Andberg <jandberg%welho.com@localhost>]

Frank Wille wrote:
> Why is coherency enabled? I'm sure all Fast RAM is bat-mapped without BAT_M.
> So it must be page-table mapped? I saw the pmap-code using PTE_M quite
> often.

Yes, it happens with page table mappings (right away when init is being
started), and also when running with address translation off in kernel (in
pmap_zero_page). In the latter case the M bit is on by default. 

> One difference for your pmap-system is that it is using Chip RAM (for the
> tables?). Maybe the cache-attributes for Chip RAM (cache-inhibited and
> guarded) do have a bad influence on the whole pmap module...?
> Just guessing - I know next to nothing about pmap. :|

Right, I found out that having page tables in non-cacheable memory does
not really work too well.

I didn't spend too much time with the chipmem solution. 
I'm trying now to get the pmap to accept fast RAM. But this is a
different problem.

> But you saw any other exceptions correctly handled on the BPPC? Or is there
> a problem with this type of exception.

At least page faults and alignment exceptions are caught normally.
 
> I remember I had a similar problem with dcbz many years ago when I started
> working on amigappc. Never found out what happened and I gave up. After
> some months with updated sources the problem was gone...

Until now! 

Well, at least disabling the coherency bit is some kind of a workaround.
 
--jukka