Subject: Re: MIPS Magnum 4000-PC fails to boot
To: Mark Abene <phiber@radicalmedia.com>
From: Jason R Thorpe <thorpej@zembu.com>
List: port-arc
Date: 11/09/2000 22:27:34
On Fri, Nov 10, 2000 at 01:09:10AM -0500, Mark Abene wrote:
> OK, do me a favor. In arch/mips/mips/locore.S, find _splnone, and change:
>
> li v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
>
> to read:
>
> li v0, ((MIPS_INT_MASK & ~MIPS_INT_MASK_4)| MIPS_SR_INT_IE)
Okay, I'll try this out tomorrow.
> both of which use an R4230 MCT ADR. The Olivetti doesn't suffer from the
> problem we're seeing, and the interval timer works just fine. I just had
> a look at the Olivetti's ARC firmware. It's different from the Magnum's,
> but so far I don't see it doing anything out of the ordinary with the
> interval timer registers.
> There's also the fact that neither the RISC/OS firmware nor the RISC/OS kernel
> make use of the interval timer. They chose to use the on-cpu timer for their
> clock interrupts. Maybe they had good reason? Maybe the R4030/4230 isn't
> wired up properly on the Magnum? Or maybe ARC isn't initializing the ASIC
> to our satisfaction? We really need to locate the tech manual for the Magnum,
> which hopefully describes the interrupt mappings, and whether the ASIC's
> interval timer->INT4 setup isn't totally broken...
>
> Let me know what happens. Also, there's no chance you actually have a 4000SC
> motherboard in a 4000PC chassis, is there? Could you check? I know it's
> silly, but I want to be sure. Also, if you could verify that you have a 4230
> in your machine.
Well, the "cpu0: no L2 cache" is kind of a giveaway :-) Where is ARCDIAG
and I'll boot it just to be sure.
The machine certainly could be a frankenstein -- I got it from a friend
who used to work at SGI, and it seems to have not-quite-stock ARCSystem
firmware (unless they all say "SGI version ..." at the top of the screen :-)
...perhaps in order to solve this, we'll have to traverse the device
tree to find the system controller and identify it by the info in
the tree node?
--
-- Jason R. Thorpe <thorpej@zembu.com>