In message <20010210234622.B1040@mail.radicalmedia.com> Mark Abene writes:
: Could you elaborate on your kludge?  What needed to be fixed exactly?
: Was the cache coherency problem with L2 cache?

cache invalidation before/after dma, at least for the affected address
range.  I think that busdma does the right thing now.  IT was for L1
cache in my case, but L2 cache that the cpu manages might be the
problem and you might not be flushing properly.  Or maybe you are and
the problem lies elsewhere.  I had a vr4102 based machine that hung in
init for one version, but a version 3 months later worked great.
There was a small chance it was build environment, so maybe that's
biting you.  The Linux/mips people like to say how buggy the mips code
generation is with binutils.

Warner