Hi,

I'm just wanting to clarify something to do with load delays, and conditional 
execution, as I understand it and ldr instruction requires 2 cycles for the 
value to be available or it stalls, also cond exec still uses up 1 cycle even 
if the instruction isn't actually executed, so in theory:

(code is from iomd_irq.S)
This:
	ldr	r6, [r7, r9, lsl #2]	/* Get address of first handler structure */
        ldr	r4, Lcnt		/* Stat info A */

	teq	r6, #0x00000000		/* Do we have a handler */
	moveq	r0, r8			/* IRQ requests as arg 0 */
	
will stall one cycle waiting for r6 to fill?

so does this mean that:
	ldr	r6, [r7, r9, lsl #2]	/* Get address of first handler structure */
        ldr	r4, Lcnt		/* Stat info A */

	mov	r0, r8			/* IRQ requests as arg 0 */
	teq	r6, #0x00000000		/* Do we have a handler */

where the value of r0 only matters if r6 == NULL, it's overwritten elsewhere 
if r6 != NULL.

would actually save 1 cycle?  Or does this turn out to depend on the 
processor?

Cheers,
Chris

(those wondering I'm working on tweaking the irq handling code for as much 
speed as possible, so every cycle saved helps, I know some'll claim I'm mad 
for doing this, but currently I've not much time, so doing small contained 
bits like this is possible)