On Sun, 11 Aug 2002, Ben Harris wrote:

> More experimentation.  I've replaced runs of STR and LDR with STM and
> LDM, tweaking the register usage in copyin to make the runs longer.  The
> diff's attached.
>
> Same test as ever: dd if=/dev/zero of=/dev/null count=1024 bs=1024k

With an extra hack, it works on 26-bit machines as well:

ARM3, 25 MHz, 4KB unified cache:
bjh21old: 1073741824 bytes transferred in 984.083 secs (1091109 bytes/sec)
bjh21:    1073741824 bytes transferred in 198.960 secs (5396772 bytes/sec)

I'll commit this in a moment (Jason seems to think this is OK).

-- 
Ben Harris                                                   <bjh21@netbsd.org>
Portmaster, NetBSD/acorn26           <URL:http://www.netbsd.org/Ports/acorn26/>