On Thu, Dec 12, 2002 at 12:41:27AM +0900, Toru Nishimura wrote:

 > That's the quite big move of ARM processor.  Virtual address tagged cache
 > is proven inadequate long time ago.  ARM camp has historically
 > paid little attention on how significant the cache machinary is to OS
 > foundation and ARM documents tend to be terse about cache systems.
 > I recently trapped by cache design change in 920T->926E.

Well, if you consider that most ARM pre-ARMv6 cores are available
in processors either with or without an MMU, then the VIVT cache
architecture makes some sense... because it effectively allows them
to "bolt the MMU to the outside".

Also, many ARM applications are in embedded systems that run in a
single address space, and those applications are not going to pay
the penalty of the cache flush on context switch.

Now, that is not to say that I don't agree with you about VIVT caches;
I personally shudder every time I have to deal with a VI cache... :-)

I wonder if any ARMv6 CPUs will come with a PU rather than an MMU...

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>