On Fri, 2005-01-07 at 10:52, Kamal R. Prasad wrote:

> Can we trap the instructions that execute
> after a tlb has been invalidated? 

Not within the core, since that would need valid TLB entries to do
further processing (catch-22).

> Why won't the
> processor throw an exception if it reads invalid data
> in the L1 cache? Im stuck in the sense there is no
> debug mechanism for me to find out why its hanging.
> Can I insert some code to be executed after the
> translation buffer has been invalidated (irrespective
> of its contents)?

If you've got access to an embedded trace box (eg multi-trace, or
RV-trace from arm --- there are probably other devices from elsewhere)
then you can stop the core and download an accurate log of what it is
trying to do.  It might (or might not, no guarantees here) tell you at
what point it is failing.

R.