On Sat, 22 Jan 2005 08:52:58 PST, Jason Thorpe wrote:
> On Jan 22, 2005, at 1:20 AM, Richard Earnshaw wrote:
> 
> > Yep, I think I've identified the problem.  The chips are in DPA mode.  
> > The
> > manual talks about moving jumpers J11-14 to their alternate position, 
> > but
> > I can't find those anywhere.
> >
> > And looking at the schematics it appears that on the Rev E boards, at
> > least, the DPA config pin is hard-wired :-( :-( :-(
> 
> Grr, that's lame.
> 
> DPA mode isn't especially difficult to support, if you ignore the SATA 
> NCQ aspects... mainly just a different register layout.  You should be 
> able to download the manual for the chip from the Intel web site.  I'm 
> pretty sure the Linux "Vitesse SATA" driver (which works with the 
> GD31244) also has support for DPA mode.
> 

Wheeee!

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005        
    The NetBSD Foundation, Inc.  All rights reserved.                           
Copyright (c) 1982, 1986, 1989, 1991, 1993                                      
    The Regents of the University of California.  All rights reserved.          
                                                                                
NetBSD 2.99.14 (IQ31244) #19: Fri Feb  4 01:14:31 GMT 2005                      
        rearnsha@merlin.buzzard.freeserve.co.uk:/work/rearnsha/netbsd/build/trunk/evbarm/src/sys/arch/evbarm/compile/IQ31244                                    
total memory = 256 MB                                                           
avail memory = 244 MB                                                           
mainbus0 (root)                                                                 
cpu0 at mainbus0: i80321 600MHz rev 2 (XScale core)                             
cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled           
cpu0: 32KB/32B 32-way Instruction cache                                         
cpu0: 32KB/32B 32-way write-back-locking Data cache                             
obio0 at mainbus0                                                               
com0 at obio0 addr 0xfe800000 xint 1: ns16550a, working fifo                    
com0: console                                                                   
iopxs0 at mainbus0: i80321 I/O Processor, acting as PCI host                    
iopxs0: configuring PCI bus                
iopaau0 at iopxs0                                                               
iopiic0 at iopxs0: I2C controller                                               
iic0 at iopiic0: I2C bus                                                        
iopiic1 at iopxs0: I2C controller                                               
iic1 at iopiic1: I2C bus                                                        
iopwdog0 at iopxs0: 7 second period                                             
pci0 at iopxs0 bus 0                                                            
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok              
ppb0 at pci0 dev 1 function 0: Intel product 0x537c (PCI bridge, revision 0x03) at ? dev 1 function 0 (intrswiz
 0, intrpin 0, i/o on, mem on, no quirks): Intel product 0x537c (rev. 0x03)     
pci1 at ppb0 bus 1                                                              
pci1: i/o space, memory space enabled, rd/line, wr/inv ok                       
artsata0 at pci1 dev 1 function 0: Intel 31244 Serial ATA Controller (SATA mass storage) at ? dev 1 function 0 (int
rswiz 0x1, intrpin 0x2, i/o on, mem on, no quirks)                              
artsata0: Intel 31244 Serial ATA Controller (rev. 0x00)                         
artsata0: interface wired in DPA mode                                           
artsata0: using irq 29 for native-PCI interrupt                                 
atabus0 at artsata0 channel 0                                                   
atabus1 at artsata0 channel 1                                                   
atabus2 at artsata0 channel 2                                                   
atabus3 at artsata0 channel 3                                                   
artsata1 at pci1 dev 2 function 0: 
[...]
wm1: interrupting at irq 27                                                     
wm1: Ethernet address 00:80:4d:01:00:e7                                         
makphy1 at wm1 phy 1: Marvell 88E1011 Gigabit PHY, rev. 3                       
makphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT, 1000baseT-FD
X, auto                                                                         
clock: hz=100 stathz=0 profhz=0                                                 
artsata0: port 0: scnt=0x1 sn=0x1 cl=0x0 ch=0x0                                 
artsata0: port 0: device present, speed: 1.5Gb/s                                
wd0 at atabus0 drive 0: <WDC WD1600JD-55HBB0>                                   
wd0: drive supports 16-sector PIO transfers, LBA48 addressing                   
wd0: 149 GB, 310101 cyl, 16 head, 63 sec, 512 bytes/sect x 312581808 sectors    
wd0: 32-bit data port                                                           
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)        
wd0(artsata0:0:0): using PIO mode 4                                             
boot device: <unknown>                                                          
root on wm0                                                                     
nfs_boot: trying DHCP/BOOTP                                                     


It wasn't quite as trivial as you suggested, in DPA mode the standard ATA command registers are wider than normal so you don't have to do previous/current operations for LBA48 mode.  That entailed some hacking in wdc.c to support the different sized register accesses.

Haven't started looking at DMA yet, but even in PIO mode, it's achieving around 6MB/s throughput...

Anyway, bed time :-)

R.