Some ARM SoC has max 64 interrupt source and known
ill-fit to conventional NetBSD/arm interrupt structure.  In specific,
bit vector recording to keep track deferred interrupts is too fragile
to do right.  It's interesting to see that such the ARM SoC provides
alternative interrupt structure to assign 'prioritized interrupt level' to
implement hierarchical relationship between groups of interrupt.
(for example, PLS consult to MC9328, or possibly EP93xx) 
Does anyone out there have insight about how the facility can be
integrated with NetBSD spl scheme?

Toru Nishimura/ALKYL Technology