> But, IIRC, that range of offsets is less for the half-word operations,
> and gcc is likely to use 32bit operations to read 16bit values (masking
> the high bits).  

Making 32bit access for 16bit quantity is as equally bad as having two
consecutive 8bit access for memory mapped I/O since it'd confuse byte
lane selector and device latch.  ARM tends to be a replacement of 8/16bit
MCU and HW designers may not well understand about endian-ness and
32bit nature of RISC discipline.  It reminds Alpha processor instruction
set has to be extended to cope with field demands for "legacy devices".

Toru Nishimura/ALKYL Technology