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Attached is a patch to add generic base support for systems based on the 
OMAP 1 family.  The devices supported in this patch are serial console 
and MPU timers for OS timing purposes.

This patch depends upon patches previously sent by Scott Allan: "Three 
small patches for ARM" on 07/26/2006 and "Patch to add support for 
ARM9E" on 07/31/2006.

A staggering number of mobile phones, PDAs, and other portable devices 
are based on these systems, and OMAP would make a great addition to 
NetBSD.  If there are any concerns we can address or other things we can 
do to get this code accepted upstream please let me know, thanks,

-- TAllan

--------------070106030305050007090906
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This patch adds base support for the OMAP.
Index: netbsd_quilt/src/sys/arch/arm/omap/files.omap
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/files.omap
@@ -0,0 +1,118 @@
+#	$NetBSD: $
+#
+# Configuration info for Texas Instruments OMAP CPU support
+# Based on xscale/files.pxa2x0
+#
+
+file	arch/arm/arm/softintr.c  # Use the generic ARM soft interrupt code.
+file	arch/arm/arm32/irq_dispatch.S
+
+# Memory size in megabytes
+defparam opt_omap.h				MEMSIZE
+
+# Texas Instruments Peripheral Bus.
+# addr: Address of the peripheral in the OMAP address space
+# size: Number of bytes that the peripheral occupies in the OMAP address space
+# intr: Interrupts connected to the first level interrupt controller should
+#	give the first level interrupt controller's number.  Interrupts
+#	connected to the second level interrupt controller should give the
+#	second level interrupt controller's number plus 32 (the number of
+#	interrupts that the first level controller has).
+# mult: Used to multiply the offsets given within a driver.  For example, if
+#	the driver expects byte registers at byte offsets, but they are mapped
+#	in at word offsets, a mult of 4 would be specified.  Note that the
+#	size parameter is not multiplied by mult.  If you specify a mult, in
+#	general, you should probably be specifying a size to ensure that the
+#	correct amount is mapped.
+device tipb { [addr=-1], [size=0], [intr=-1], [mult=1] } : bus_space_generic
+attach tipb at mainbus
+file	arch/arm/omap/omap_tipb.c		tipb
+defparam opt_omap.h				OMAP_TIPB_PBASE OMAP_TIPB_SIZE
+
+# Extended Memory Interface Slow
+# Same parameters as for TIPB, but with the addition of parameters to
+# configure bus access.  A parameter is provided to to force halfword access
+# instead of byte accesses:
+#    nobyteacc: Allow 8-bit access for device with no lsb address line
+# If this is set to 1, if an attempt is made to write a single byte to the
+# bus, it will automatically get converted into reading a halfword, setting
+# the byte that is being written into the appropriate byte of the halfword,
+# and then writing the halfword to the bus.
+#
+# In addition to the nobyteacc parameter, a number of parameters are provided
+# to configure bus timing via the EMIFS_CCS and EMIFS_ACS registers.  The cs
+# parameter specifies which chip-select should have its configuration
+# modified.
+#
+# NOTE: If the cs parameter is not specified, the EMIFS_CCS and EMIFS_ACS
+# registers will not be modified and all of the bus timing parameters will be
+# ignored.
+#
+# When cs is specified, EMIFS_CCS and EMIFS_ACS will be modified.  In addition
+# to cs on your emifs device, you must specify the base parameter on the emifs
+# bus to tell it where its registers are.  All fields of the EMIFS_CCS and
+# EMIFS_ACS registers will be set.  The EMIFS will be set to be:
+#
+#	asynchronous, non-page mode (RDMODE = 0)
+#	non-multiplexed protocol
+#	16 bit wide
+#	REF_CLK = TC_CK / 1
+#
+# The timing parameters are rdwst, oesetup, oehold, wrwst, welen, advhold,
+# btwst and btmode.  All of them specify a number of nanoseconds, except
+# btmode which is a simple 0/1 flag.
+#
+# For a read cycle, CS will be held low for rdwst nanoseconds.  The delay from
+# driving CS low to driving OE low is specified by oesetup.  OE will go back
+# high oehold nanoseconds before CS goes back high.
+#
+# For a write cycle, CS will be held low for wrwst (time before WE goes low) +
+# welen (time WE is held low) + 1 REF_CLK cycle (time after WE goes high).
+#
+# For both read and write, advhold specifies how long ADV should be remain low
+# after it is driven low at the same time as CS.
+#
+# The bus turn around time (amount of time that CS needs to be high between
+# accesses) is specified by btwst and btmode.  See the TRM for more
+# information.
+#
+# If btmode is not specified, it will be set to 0.  All other timing
+# parameters will default to their minimum value.
+#
+device emifs { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0],
+	       [cs=-1], [rdwst=0], [oesetup=0], [oehold=0],
+	       [wrwst=0], [welen=0], [advhold=0], [btwst=0], [btmode=0]
+	     } : bus_space_generic
+attach emifs at mainbus
+file	arch/arm/omap/omap_emifs.c		emifs
+file	arch/arm/omap/omap_nobyteacc_space.c	emifs
+file	arch/arm/omap/omap_nobyteacc_io.S	emifs
+defparam opt_omap.h				OMAP_TC_CLOCK_FREQ
+
+# OCP
+device ocp { [addr=-1], [size=0], [intr=-1], [mult=1]} : bus_space_generic
+attach ocp at mainbus
+file	arch/arm/omap/omap_ocp.c		ocp
+
+# TIPB/EMIFS/OCP common files
+file	arch/arm/omap/omap_space.c		tipb | emifs | ocp
+file	arch/arm/omap/omap_a2x_space.c		tipb | emifs | ocp
+file	arch/arm/omap/omap_a2x_io.S		tipb | emifs | ocp
+file	arch/arm/omap/omap_a4x_space.c		tipb | emifs | ocp
+file	arch/arm/xscale/pxa2x0_a4x_io.S		tipb | emifs | ocp
+
+# NS16550 compatible serial ports
+attach com at tipb with omapuart
+file	arch/arm/omap/omap_com.c		omapuart
+defparam opt_com.h				CONSADDR CONSPEED CONMODE
+
+# INTC controller
+define omapintc
+file	arch/arm/omap/omap_intr.c		omapintc
+
+# MPU Timer
+device omapmputmr
+attach omapmputmr at tipb
+file	arch/arm/omap/omap_mputmr.c		omapmputmr
+defparam opt_omap.h				OMAP_MPU_TIMER_CLOCK_FREQ
+
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_reg.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_reg.h
@@ -0,0 +1,42 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_OMAP_OMAP_REG_H_
+#define _ARM_OMAP_OMAP_REG_H_
+
+#include "opt_omap.h"
+
+#ifndef MEMSIZE
+#error Specify the amount of SDRAM in megabytes with the MEMSIZE option.
+#endif
+#define MEMSIZE_BYTES (MEMSIZE * 1024 * 1024)
+
+#ifndef OMAP_TIPB_PBASE
+#error Specify the TIPB physical address with the OMAP_TIPB_PBASE option.
+#endif
+#ifndef OMAP_TIPB_SIZE
+#error Specify the TIPB size with the OMAP_TIPB_SIZE option.
+#endif
+
+#endif /* _ARM_OMAP_OMAP_REG_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_tipb.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_tipb.h
@@ -0,0 +1,44 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_OMAP_OMAP_TIPB_H_
+#define _ARM_OMAP_OMAP_TIPB_H_
+
+/* Texas Instruments Peripheral Bus */
+
+struct tipb_attach_args {
+	bus_space_tag_t	tipb_iot;	/* Bus tag */
+	bus_addr_t	tipb_addr;	/* Address */
+	bus_size_t	tipb_size;	/* Size of peripheral address space */
+	int		tipb_intr;	/* IRQ number */
+	bus_dma_tag_t	tipb_dmac;	/* DMA channel */
+	int		tipb_mult;	/* Offset multiplier */
+};
+
+extern struct bus_space omap_bs_tag;
+extern struct arm32_bus_dma_tag omap_bus_dma_tag;
+extern struct bus_space omap_a4x_bs_tag;
+extern struct bus_space omap_a2x_bs_tag;
+
+#endif /* _ARM_OMAP_OMAP_TIPB_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_tipb.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_tipb.c
@@ -0,0 +1,275 @@
+/*	$NetBSD: $ */
+
+/*
+ * Autoconfiguration support for the Texas Instruments OMAP TIPB.
+ * Based on arm/xscale/pxa2x0.c which in turn was derived from
+ * arm/sa11x0/sa11x0.c.  The code to do the early attach was initially derived
+ * from arch/sparc/dev/obio.c.
+ *
+ * Copyright (c) 2002, 2005  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Copyright (c) 1999
+ *         Shin Takemura and PocketBSD Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the PocketBSD project
+ *	and its contributors.
+ * 4. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 1997,1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include "locators.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+
+#include <arm/cpufunc.h>
+#include <arm/mainbus/mainbus.h>
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_tipb.h>
+
+struct tipb_softc {
+	struct device sc_dev;
+	bus_dma_tag_t sc_dmac;
+};
+
+/* prototypes */
+static int	tipb_match(struct device *, struct cfdata *, void *);
+static void	tipb_attach(struct device *, struct device *, void *);
+static int 	tipb_search(struct device *, struct cfdata *,
+			     const int *, void *);
+static int	tipb_print(void *, const char *);
+
+/* attach structures */
+CFATTACH_DECL(tipb, sizeof(struct tipb_softc),
+    tipb_match, tipb_attach, NULL, NULL);
+
+static int tipb_attached;
+
+/*
+ * There are some devices that need to be set up before all the others.  The
+ * earlies array contains their names.  tipb_attach() and tipb_search() work
+ * together to attach these devices in the order they appear in this array
+ * before any other TIPB devices are attached.
+ */
+static const char * const earlies[] = {
+	OMAP_INTC_DEVICE,
+	"omapmputmr",
+	NULL
+};
+
+static int
+tipb_match(struct device *parent, struct cfdata *match, void *aux)
+{
+	if (tipb_attached)
+		return 0;
+	return 1;
+}
+
+static void
+tipb_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct tipb_softc *sc = (struct tipb_softc *)self;
+
+	tipb_attached = 1;
+
+#if NOMAPDMAC > 0
+#error DMA not implemented
+	sc->sc_dmac = &omap_bus_dma_tag;
+#else
+	sc->sc_dmac = NULL;
+#endif
+
+	aprint_normal(": Texas Instruments Peripheral Bus\n");
+	aprint_naive("\n");
+
+	/*
+	 * There are some devices that need to be set up before all the
+	 * others.  The earlies array contains their names.  Find them and
+	 * attach them in the order they appear in the array.
+	 */
+	const char *const *earlyp;
+	for (earlyp = earlies; *earlyp != NULL; earlyp++)
+		/*
+		 * The bus search function is passed an aux argument that
+		 * "describes the device that has been found".  The type of it
+		 * is void *.  However, I want to pass a constant string, so
+		 * use __UNCONST to convince the compiler that this is ok.
+		 */
+		config_search_ia(tipb_search, self, "tipb",
+				 __UNCONST(*earlyp));
+
+	/*
+	 * Attach all other devices
+	 */
+	config_search_ia(tipb_search, self, "tipb", NULL);
+}
+
+static int
+tipb_search(struct device *parent, struct cfdata *cf,
+	     const int *ldesc, void *aux)
+{
+	struct tipb_softc *sc = (struct tipb_softc *)parent;
+	struct tipb_attach_args aa;
+	const char *const name = (const char *const)aux;
+
+	/* Check whether we're looking for a specifically named device */
+	if (name != NULL && strcmp(name, cf->cf_name) != 0)
+		return (0);
+
+	switch (cf->cf_loc[TIPBCF_MULT]) {
+	case 1:
+		aa.tipb_iot = &omap_bs_tag;
+		break;
+	case 2:
+		aa.tipb_iot = &omap_a2x_bs_tag;
+		break;
+	case 4:
+		aa.tipb_iot = &omap_a4x_bs_tag;
+		break;
+	default:
+		panic("Unsupported TIPB multiplier.");
+		break;
+	}
+	aa.tipb_dmac = sc->sc_dmac;
+	aa.tipb_addr = cf->cf_loc[TIPBCF_ADDR];
+	aa.tipb_size = cf->cf_loc[TIPBCF_SIZE];
+	aa.tipb_intr = cf->cf_loc[TIPBCF_INTR];
+	aa.tipb_mult = cf->cf_loc[TIPBCF_MULT];
+
+	if (config_match(parent, cf, &aa))
+		config_attach(parent, cf, &aa, tipb_print);
+
+	return 0;
+}
+
+static int
+tipb_print(void *aux, const char *name)
+{
+	struct tipb_attach_args *sa = (struct tipb_attach_args*)aux;
+
+	if (sa->tipb_addr != TIPBCF_ADDR_DEFAULT) {
+		aprint_normal(" addr 0x%08lx", sa->tipb_addr);
+		if (sa->tipb_size > TIPBCF_SIZE_DEFAULT)
+			aprint_normal("-0x%08lx", sa->tipb_addr + sa->tipb_size-1);
+	}
+	if (sa->tipb_intr != TIPBCF_INTR_DEFAULT)
+		aprint_normal(" intr %d", sa->tipb_intr);
+
+	return (UNCONF);
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_a4x_space.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_a4x_space.c
@@ -0,0 +1,136 @@
+/*	$NetBSD: $ */
+
+/*
+ * Based on arch/arm/xscale/pxa2x0_a4x_space.c
+ *
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Bus space tag for 8/16-bit devices on 32-bit bus.
+ * all registers are located at the address of multiple of 4.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(omap);
+bs_protos(a4x);
+bs_protos(bs_notimpl);
+
+struct bus_space omap_a4x_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	omap_bs_map,
+	omap_bs_unmap,
+	omap_bs_subregion,
+
+	/* allocation/deallocation */
+	omap_bs_alloc,	/* not implemented */
+	omap_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	omap_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	omap_bs_barrier,
+
+	/* read (single) */
+	a4x_bs_r_1,
+	a4x_bs_r_2,
+	a4x_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	a4x_bs_rm_1,
+	a4x_bs_rm_2,
+	bs_notimpl_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	bs_notimpl_bs_rr_1,
+	bs_notimpl_bs_rr_2,
+	bs_notimpl_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	a4x_bs_w_1,
+	a4x_bs_w_2,
+	a4x_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	a4x_bs_wm_1,
+	a4x_bs_wm_2,
+	bs_notimpl_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	bs_notimpl_bs_wr_1,
+	bs_notimpl_bs_wr_2,
+	bs_notimpl_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	bs_notimpl_bs_sr_1,
+	bs_notimpl_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	bs_notimpl_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+
+
+
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_intr.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_intr.h
@@ -0,0 +1,214 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file used pxa2x0_intr.h as a template, but now bears little semblance
+ * to it.  In its new form, it should not be included directly.  Rather, it
+ * should only be included from an include file that is specific to a
+ * particular OMAP (e.g. omap5912_intr.h).  That file will define the
+ * information that varies from OMAP to OMAP and then includes this file to
+ * provide the OMAP generic information.  As more OMAP ports are done, more
+ * information may need to move from this file out into the particular OMAP
+ * header files.
+ */
+
+#ifndef _ARM_OMAP_OMAP_INTR_H_
+#define _ARM_OMAP_OMAP_INTR_H_
+
+#define	ARM_IRQ_HANDLER	_C_LABEL(omap_irq_handler)
+
+#ifndef _LOCORE
+
+#include <arm/cpu.h>
+#include <arm/armreg.h>
+#include <arm/cpufunc.h>
+#include <machine/atomic.h>
+#include <arm/softintr.h>
+
+#define OMAP_IRQ_MIN			0
+#define OMAP_NIRQ			(OMAP_INT_L1_NIRQ + OMAP_INT_L2_NIRQ)
+#define OMAP_BANK_WIDTH			(32)
+#if (OMAP_NIRQ & (OMAP_BANK_WIDTH - 1))
+#error OMAP_NIRQ must be an even multiple of OMAP_BANK_WIDTH
+#endif
+#define OMAP_NBANKS			(OMAP_NIRQ / OMAP_BANK_WIDTH)
+
+/* Offsets within the OMAP interrupt controllers */
+#define OMAP_INTC_SIR_IRQ	0x10	/* Interrupt source register (IRQ) */
+#define OMAP_INTC_SIR_FIQ	0x14	/* Interrupt source register (FIQ) */
+/* These registers differ in meaning between L1 and L2 controllers */
+#define OMAP_INTL1_CONTROL	0x18	/* Interrupt control register */
+#define  OMAP_INTL1_CONTROL_NEW_FIQ_AGR		(1<<1)
+#define  OMAP_INTL1_CONTROL_NEW_IRQ_AGR		(1<<0)
+#define OMAP_INTL1_GMR		0xA0	/* Global mask interrupt register */
+#define  OMAP_INTL1_GMR_GLOBAL_MASK			(1<<0)
+#define OMAP_INTL2_CONTROL	0x18	/* Interrupt control register */
+#define  OMAP_INTL2_CONTROL_GLOBAL_MASK		(1<<2)
+#define  OMAP_INTL2_CONTROL_NEW_FIQ_AGR		(1<<1)
+#define  OMAP_INTL2_CONTROL_NEW_IRQ_AGR		(1<<0)
+#define OMAP_INTL2_STATUS	0xA0	/* Status register */
+#define  OMAP_INTL2_STATUS_RESET_DONE		(1<<0)
+#define OMAP_INTL2_OCP_CFG	0xA4	/* OCP configuration register */
+#define  OMAP_INTL2_OCP_CFG_FORCE_WAKEUP	(0<<3)
+#define  OMAP_INTL2_OCP_CFG_SMART_IDLE		(2<<3)
+#define  OMAP_INTL2_OCP_CFG_SOFTRESET		(1<<1)
+#define  OMAP_INTL2_OCP_CFG_AUTOIDLE		(1<<0)
+#define OMAP_INTL2_INTH_REV	0xA8	/* Interrupt controller revision ID */
+#define  OMAP_INTL2_INTH_REV_MAJOR(r)		(((r)&0xF0)>>4)
+#define  OMAP_INTL2_INTH_REV_MINOR(r)		((r)&0x0F)
+#define OMAP_INTL2_BANK_OFF	0x100	/* Offset between each bank. */
+
+
+/* Offsets within the banks of the OMAP interrupt controllers */
+#define OMAP_INTB_ITR		0x00	/* Interrupt register */
+#define OMAP_INTB_MIR		0x04	/* Interrupt mask register */
+#define OMAP_INTB_ILR_BASE	0x1C	/* Interrupt priority level register */
+#define  OMAP_INTB_ILR_PRIO_SHIFT		2
+#define  OMAP_INTB_ILR_PRIO_LOWEST		31	/* L2's really 127 */
+#define  OMAP_INTB_ILR_PRIO_HIGHEST		0
+#define  OMAP_INTB_ILR_EDGE			(0<<1)
+#define  OMAP_INTB_ILR_LEVEL			(1<<1)
+#define  OMAP_INTB_ILR_IRQ			(0<<0)
+#define  OMAP_INTB_ILR_FIQ			(1<<0)
+#define OMAP_INTB_SISR		0x9C	/* Software interrupt set register */
+
+/* Array of structures that allow us to get per interrupt constants. */
+typedef enum {
+    /* 0 in this field marks a reserved interrupt that should not be used. */
+    INVALID = 0,
+    TRIG_LEVEL,
+    TRIG_EDGE,
+    TRIG_LEVEL_OR_EDGE
+} omap_intr_trig_t;
+typedef struct {
+	omap_intr_trig_t trig;
+	vaddr_t bank_base;
+	int bank_num;
+	vaddr_t ILR;
+	uint32_t mask;
+} omap_intr_info_t;
+extern const omap_intr_info_t omap_intr_info[OMAP_NIRQ];
+
+/* Array of pointers to each bank's base. */
+extern vaddr_t omap_intr_bank_bases[OMAP_NBANKS];
+
+/* Array of arrays to give us the per bank masks for each level. */
+extern uint32_t omap_spl_masks[NIPL][OMAP_NBANKS];
+/* Array of globally-off masks while interrupts processed. */
+extern uint32_t omap_global_masks[OMAP_NBANKS];
+
+/* Array to translate from software interrupt numbers to an irq number. */
+extern int omap_si_to_irq[OMAP_FREE_IRQ_NUM];
+
+extern volatile int current_spl_level;
+
+/*
+ * Direct access is being done because 1) it's faster and 2) the interrupt
+ * controller code is still very tied to the OMAP so we don't really have
+ * the concept of going through a bus at an address specified in the config.
+ */
+#define read_icu(base,offset) (*(volatile uint32_t *)((base)+(offset)))
+#define write_icu(base,offset,value) \
+ (*(volatile uint32_t *)((base)+(offset))=(value))
+
+static inline void
+omap_splx(int new)
+{
+	vaddr_t *bases = &omap_intr_bank_bases[0];
+	uint32_t *masks = &omap_spl_masks[new][0];
+	int psw = disable_interrupts(I32_bit);
+
+	current_spl_level = new;
+
+#if OMAP_NBANKS != 5
+#error Revisit loop unrolling in omap_splx()
+#endif
+	write_icu(bases[0], OMAP_INTB_MIR, masks[0] | omap_global_masks[0]);
+	write_icu(bases[1], OMAP_INTB_MIR, masks[1] | omap_global_masks[1]);
+	write_icu(bases[2], OMAP_INTB_MIR, masks[2] | omap_global_masks[2]);
+	write_icu(bases[3], OMAP_INTB_MIR, masks[3] | omap_global_masks[3]);
+	write_icu(bases[4], OMAP_INTB_MIR, masks[4] | omap_global_masks[4]);
+	restore_interrupts(psw);
+}
+
+static inline int
+omap_splraise(int ipl)
+{
+	int old = current_spl_level;
+	if (ipl > current_spl_level)
+		omap_splx(ipl);
+	return (old);
+}
+
+static inline int
+omap_spllower(int ipl)
+{
+	int old = current_spl_level;
+	omap_splx(ipl);
+	return(old);
+}
+
+static inline void
+omap_setsoftintr(int si)
+{
+	const omap_intr_info_t *info;
+
+	KDASSERT(si < OMAP_FREE_IRQ_NUM);
+
+	int irqno = omap_si_to_irq[si];
+	KDASSERT(irqno >= OMAP_IRQ_MIN);
+	KDASSERT(irqno < OMAP_NIRQ);
+
+	info = &omap_intr_info[irqno];
+	KDASSERT(info->trig != INVALID);
+
+#if OMAP_INT_FREE1 < OMAP_INT_L1_NIRQ
+	/* Level 1 Interrupt Controller needs a zero before the one. */
+	write_icu(info->bank_base, OMAP_INTB_SISR, 0);
+#endif
+	write_icu(info->bank_base, OMAP_INTB_SISR, info->mask);
+}
+
+
+int	_splraise(int);
+int	_spllower(int);
+void	splx(int);
+void	_setsoftintr(int);
+
+#if !defined(EVBARM_SPL_NOINLINE)
+#define splx(new)		omap_splx(new)
+#define	_spllower(ipl)		omap_spllower(ipl)
+#define	_splraise(ipl)		omap_splraise(ipl)
+#define	_setsoftintr(si)	omap_setsoftintr(si)
+#endif	/* !EVBARM_SPL_NOINTR */
+
+void omap_irq_handler(void *);
+void *omap_intr_establish(int, int, const char *, int (*)(void *), void *);
+void omap_intr_disestablish(void *);
+int omapintc_match(struct device *, struct cfdata *, void *);
+void omapintc_attach(struct device *, struct device *, void *);
+
+#endif /* ! _LOCORE */
+
+#endif /* _ARM_OMAP_OMAP_INTR_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_com.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_com.c
@@ -0,0 +1,131 @@
+/*	$NetBSD: $	*/
+
+/*
+ * Based on arch/arm/xscale/pxa2x0_com.c
+ *
+ * Copyright 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed for the NetBSD Project by
+ *      Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include "opt_com.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/termios.h>
+
+#include <machine/intr.h>
+#include <machine/bus.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_tipb.h>
+#include <arm/omap/omap_com.h>
+
+#include "locators.h"
+
+static int	omapuart_match(struct device *, struct cfdata *, void *);
+static void	omapuart_attach(struct device *, struct device *, void *);
+
+CFATTACH_DECL(omapuart, sizeof(struct com_softc),
+    omapuart_match, omapuart_attach, NULL, NULL);
+
+static int
+omapuart_match(struct device *parent, struct cfdata *cf, void *aux)
+{
+	struct tipb_attach_args *tipb = aux;
+	bus_space_handle_t bh;
+	int rv;
+
+	if (tipb->tipb_addr == -1 || tipb->tipb_intr == -1)
+	    panic("omapuart must have addr and intr specified in config.");
+
+	if (tipb->tipb_size == 0)
+		tipb->tipb_size = OMAP_COM_SIZE;
+
+	if (com_is_console(tipb->tipb_iot, tipb->tipb_addr, NULL))
+		return (1);
+
+	if (bus_space_map(tipb->tipb_iot, tipb->tipb_addr, tipb->tipb_size,
+			  0, &bh))
+		return (0);
+
+	/*
+	 * The TRM says the mode should be disabled while dll and dlh are
+	 * being changed so we disable before probing, then enable.
+	 */
+	bus_space_write_1(tipb->tipb_iot, bh,
+			  OMAP_COM_MDR1, OMAP_COM_MDR1_MODE_DISABLE);
+
+	rv = comprobe1(tipb->tipb_iot, bh);
+
+	bus_space_write_1(tipb->tipb_iot, bh,
+			  OMAP_COM_MDR1, OMAP_COM_MDR1_MODE_UART_16X);
+
+	bus_space_unmap(tipb->tipb_iot, bh, tipb->tipb_size);
+
+	return (rv);
+}
+
+static void
+omapuart_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct com_softc *sc = (struct com_softc *)self;
+	struct tipb_attach_args *tipb = aux;
+	bus_space_tag_t iot;
+	bus_space_handle_t ioh;
+	bus_addr_t iobase;
+
+	iot = tipb->tipb_iot;
+	iobase = tipb->tipb_addr;
+	sc->sc_frequency = OMAP_COM_FREQ;
+	sc->sc_type = COM_TYPE_NORMAL;
+
+	if (com_is_console(iot, iobase, &ioh) == 0 &&
+	    bus_space_map(iot, iobase, tipb->tipb_size, 0, &ioh)) {
+		panic(": can't map registers\n");
+		return;
+	}
+	COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
+
+	com_attach_subr(sc);
+	aprint_naive("\n");
+
+	omap_intr_establish(tipb->tipb_intr, IPL_SERIAL, sc->sc_dev.dv_xname,
+			    comintr, sc);
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_intr.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_intr.c
@@ -0,0 +1,547 @@
+/*	$NetBSD: $	*/
+
+/*
+ * Based on arch/arm/xscale/pxa2x0_intr.c
+ *
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * IRQ handler for the Texas Instruments OMAP processors.  The OMAPs
+ * have two cascaded interrupt controllers.  They have similarities, but
+ * are not identical.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <machine/lock.h>
+
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_tipb.h>
+
+/*
+ * Array of arrays to give us the per bank masks for each level.  The OMAP
+ * interrupt controller blocks an interrupt when the corresponding bit is set
+ * in the mask register.  Initialize our masks to have all interrupts blocked
+ * for all levels.
+ */
+uint32_t omap_spl_masks[NIPL][OMAP_NBANKS] =
+	{ [ 0 ... NIPL-1 ] = { [ 0 ... OMAP_NBANKS-1 ] = ~0 } };
+
+/*
+ * And OR in the following global interrupt masks at all levels.  This is
+ * used to hold off interrupts that omap_irq_handler will soon service,
+ * since servicing is performed in random order wrt spl levels.
+ */
+
+uint32_t omap_global_masks[OMAP_NBANKS];
+
+/* Array to translate from software interrupt number to priority level. */
+static const int si_to_ipl[SI_NQUEUES] = {
+	IPL_SOFT,		/* SI_SOFT */
+	IPL_SOFTCLOCK,		/* SI_SOFTCLOCK */
+	IPL_SOFTNET,		/* SI_SOFTNET */
+	IPL_SOFTSERIAL,		/* SI_SOFTSERIAL */
+};
+
+static int stray_interrupt(void *);
+static int soft_interrupt(void *);
+static void init_interrupt_masks(void);
+static void omap_update_intr_masks(int, int);
+static void omapintc_set_name(int, const char *, int);
+
+typedef int (* omap_irq_handler_t)(void *);
+
+/*
+ * interrupt dispatch table.
+ */
+#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
+struct intrhand {
+	TAILQ_ENTRY(intrhand) ih_list;	/* link on intrq list */
+	int (*ih_func)(void *);		/* handler */
+	void *ih_arg;			/* arg for handler */
+};
+#endif
+
+static struct irq_handler {
+	struct evcnt ev;
+	char irq_num_str[8];
+	const char *name;
+#ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
+	TAILQ_HEAD(,intrhand) list;
+#else
+	omap_irq_handler_t func;
+#endif
+	void *cookie;		/* NULL for stack frame */
+	/* struct evbnt ev; */
+} handler[OMAP_NIRQ];
+
+volatile int current_spl_level;
+static int extirq_level[OMAP_NIRQ];
+
+int
+omapintc_match(struct device *parent, struct cfdata *cf, void *aux)
+{
+	return (1);
+}
+
+void
+omapintc_attach(struct device *parent, struct device *self, void *args)
+{
+	int i;
+	aprint_normal(": Interrupt Controller\n");
+	aprint_naive("\n");
+
+	/* Make sure we have interrupts globally off. */
+	disable_interrupts(I32_bit);
+
+	/*
+	 * Initialize the controller hardware.
+	 */
+	/* Turn off the first level's global mask. */
+	write_icu(OMAP_INT_L1_BASE, OMAP_INTL1_GMR, 0);
+	/* Turn off the second level's global mask. */
+	write_icu(OMAP_INT_L2_BASE, OMAP_INTL2_CONTROL, 0);
+	/* Allow the second level to automatically idle. */
+	write_icu(OMAP_INT_L2_BASE, OMAP_INTL2_OCP_CFG,
+	    OMAP_INTL2_OCP_CFG_SMART_IDLE | OMAP_INTL2_OCP_CFG_AUTOIDLE);
+	/*
+	 * Now set all of the Interrupt Level Registers.  Set the triggering
+	 * as appropriate for that interrupt, but otherwise, set them all to
+	 * low priority and to be an IRQ (not a FIQ).
+	 */
+	static const uint32_t ilr_def
+	    = ((OMAP_INTB_ILR_PRIO_LOWEST << OMAP_INTB_ILR_PRIO_SHIFT)
+	       | OMAP_INTB_ILR_IRQ);
+	for (i=0; i<OMAP_NIRQ; i++) {
+		const omap_intr_info_t *inf = &omap_intr_info[i];
+		volatile uint32_t *ILR = (volatile uint32_t *)inf->ILR;
+
+		switch (inf->trig) {
+		case INVALID:
+			break;
+		case TRIG_LEVEL:
+			*ILR = ilr_def | OMAP_INTB_ILR_LEVEL;
+			break;
+		case TRIG_EDGE:
+		case TRIG_LEVEL_OR_EDGE:
+			*ILR = ilr_def | OMAP_INTB_ILR_EDGE;
+			break;
+		default:
+			panic("Bad trigger (%d) on irq %d\n", inf->trig, i);
+			break;
+		}
+	}
+
+	/* Set all interrupts to be stray and to have event counters. */
+	omapintc_set_name(OMAP_INT_L2_IRQ, "IRQ from L2", FALSE);
+	omapintc_set_name(OMAP_INT_L2_FIQ, "FIQ from L2", FALSE);
+	omapintc_set_name(omap_si_to_irq[SI_SOFT], "SOFT", FALSE);
+	omapintc_set_name(omap_si_to_irq[SI_SOFTCLOCK], "SOFTCLOCK", FALSE);
+	omapintc_set_name(omap_si_to_irq[SI_SOFTNET], "SOFTNET", FALSE);
+	omapintc_set_name(omap_si_to_irq[SI_SOFTSERIAL], "SOFTSERIAL", FALSE);
+	for(i = 0; i < __arraycount(handler); ++i) {
+		handler[i].func = stray_interrupt;
+		handler[i].cookie = (void *)(intptr_t) i;
+		extirq_level[i] = IPL_SERIAL;
+		sprintf(handler[i].irq_num_str, "#%d", i);
+		if (handler[i].name == NULL)
+			omapintc_set_name(i, handler[i].irq_num_str, FALSE);
+	}
+	/* and then set up the software interrupts. */
+	for(i = 0; i < __arraycount(omap_si_to_irq); ++i) {
+		int irq = omap_si_to_irq[i];
+		handler[irq].func = soft_interrupt;
+		/* Cookie value zero means pass interrupt frame instead */
+		handler[irq].cookie = (void *)(intptr_t) (i | 0x80000000);
+		if (i < __arraycount(si_to_ipl))
+			extirq_level[irq] = si_to_ipl[i];
+		else
+			extirq_level[irq] = IPL_SOFT;
+	}
+
+	/* Initialize our table of masks. */
+	init_interrupt_masks();
+
+	/*
+	 * Now that we have the masks for all the levels set up, write the
+	 * masks to the hardware.
+	 */
+	omap_splx(IPL_SERIAL);
+
+	/* Everything is all set.  Enable the interrupts. */
+	enable_interrupts(I32_bit);
+}
+
+static void
+dispatch_irq(int irqno, struct clockframe *frame)
+{
+	if (extirq_level[irqno] != current_spl_level)
+		splx(extirq_level[irqno]);
+
+#ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
+	(* handler[irqno].func)(handler[irqno].cookie == 0
+				? frame : handler[irqno].cookie );
+#else
+		/* process all handlers for this interrupt. */
+#error Having multiple handlers per IRQ is not yet supported.
+#endif
+}
+
+/*
+ * called from irq_entry.
+ */
+void
+omap_irq_handler(void *arg)
+{
+	struct clockframe *frame = arg;
+	int saved_spl_level;
+	int unmaskedpend[OMAP_NBANKS];
+	int bank;
+	int level2 = 0;
+
+	saved_spl_level = current_spl_level;
+
+	for (bank = 0; bank < OMAP_NBANKS; bank++) {
+		int masked = read_icu(omap_intr_bank_bases[bank],
+				      OMAP_INTB_MIR);
+		int pend = read_icu(omap_intr_bank_bases[bank],
+				    OMAP_INTB_ITR);
+		/*
+		 * Save away pending unmasked interrupts for handling in
+		 * a moment.  Mask those interrupts, will unmask after
+		 * serviced.
+		 */
+
+		unmaskedpend[bank] = pend & ~masked;
+		write_icu(omap_intr_bank_bases[bank], OMAP_INTB_ITR,
+			  ~unmaskedpend[bank]);
+		write_icu(omap_intr_bank_bases[bank], OMAP_INTB_MIR,
+			  masked | unmaskedpend[bank]);
+		omap_global_masks[bank] |= unmaskedpend[bank];
+
+		/*
+		 * If any interrupt is pending for the Level-2 controller
+		 * then we need a Level-2 new IRQ agreement to receive
+		 * another one.
+		 */
+
+		if (bank && pend)
+			level2 = 1;
+	}
+
+	/* Let the interrupt controllers process the next interrupt.
+	   Acknowledge Level-1 IRQs. */
+	write_icu(OMAP_INT_L1_BASE, OMAP_INTL1_CONTROL,
+		  OMAP_INTL1_CONTROL_NEW_IRQ_AGR);
+
+	if (level2) {
+		    /* Acknowledge Level-2 IRQs. */
+		write_icu(OMAP_INT_L2_BASE, OMAP_INTL2_CONTROL,
+			  OMAP_INTL2_CONTROL_NEW_IRQ_AGR);
+	}
+
+	/*
+	 * Invoke handlers for interrupts found pending and unmasked
+	 * above.  Unmask the interrupts for each bank after servicing.
+	 */
+
+	for (bank = 0; bank < OMAP_NBANKS; bank++) {
+		int irqno;
+		int oldirqstate;
+		int pendtodo = unmaskedpend[bank];
+
+		if (!unmaskedpend[bank])
+		    continue;
+
+		while ((irqno = ffs(pendtodo) - 1) != -1) {
+			irqno += bank * OMAP_BANK_WIDTH;
+
+			if (omap_intr_info[irqno].trig == INVALID)
+				printf("Bad IRQ %d.\n", irqno);
+
+			handler[irqno].ev.ev_count++;
+
+			if (irqno != OMAP_INT_L2_IRQ) {
+				oldirqstate = enable_interrupts(I32_bit);
+				dispatch_irq(irqno, frame);
+				restore_interrupts(oldirqstate);
+			}
+
+			pendtodo &= ~omap_intr_info[irqno].mask;
+		}
+
+		omap_global_masks[bank] &= ~unmaskedpend[bank];
+		write_icu(omap_intr_bank_bases[bank], OMAP_INTB_MIR,
+			  read_icu(omap_intr_bank_bases[bank],
+				   OMAP_INTB_MIR) &
+			  ~unmaskedpend[bank]);
+	}
+
+	/* Restore spl to what it was when this interrupt happened. */
+	splx(saved_spl_level);
+}
+
+static int
+stray_interrupt(void *cookie)
+{
+	int irqno = (int)cookie;
+	printf("stray interrupt number %d: \"%s\".\n",
+	       irqno, handler[irqno].name);
+
+	if (OMAP_IRQ_MIN <= irqno && irqno < OMAP_NIRQ){
+		/* Keep it from happening again. */
+		omap_update_intr_masks(irqno, IPL_NONE);
+	}
+
+	return 0;
+}
+
+static int
+soft_interrupt(void *cookie)
+{
+	int si = (int)cookie & ~(0x80000000);
+
+	softintr_dispatch(si);
+
+	return 0;
+}
+
+
+
+static inline void
+level_block_irq(int lvl, const omap_intr_info_t *inf)
+{
+	omap_spl_masks[lvl][inf->bank_num] |= inf->mask;
+}
+static inline void
+level_allow_irq(int lvl, const omap_intr_info_t *inf)
+{
+	omap_spl_masks[lvl][inf->bank_num] &= ~inf->mask;
+}
+static inline void
+level_mask_level(int dst_level, int src_level)
+{
+	int i;
+	for (i = 0; i < OMAP_NBANKS; i++) {
+		omap_spl_masks[dst_level][i]
+		    |= omap_spl_masks[src_level][i];
+	}
+}
+
+/*
+ * Interrupt Mask Handling
+ */
+
+static void
+omap_update_intr_masks(int irqno, int level)
+{
+	const omap_intr_info_t *irq_inf =&omap_intr_info[irqno];
+	int i;
+	int psw = disable_interrupts(I32_bit);
+
+	for(i = 0; i < level; ++i)
+		/* Enable interrupt at lower level */
+		level_allow_irq(i, irq_inf);
+
+	for( ; i < NIPL-1; ++i)
+		/* Disable interrupt at upper level */
+		level_block_irq(i, irq_inf);
+
+	/*
+	 * There is no way for interrupts to be enabled at upper levels, but
+	 * not at lower levels and vice-versa.  This means that this function
+	 * doesn't have to enforce it.
+	 */
+
+	/* Refresh the hardware's masks in case the current level's changed. */
+	omap_splx(current_spl_level);
+
+	restore_interrupts(psw);
+}
+
+
+static void
+init_interrupt_masks(void)
+{
+	const omap_intr_info_t
+	    *soft_inf      =&omap_intr_info[omap_si_to_irq[SI_SOFT]],
+	    *softclock_inf =&omap_intr_info[omap_si_to_irq[SI_SOFTCLOCK]],
+	    *softnet_inf   =&omap_intr_info[omap_si_to_irq[SI_SOFTNET]],
+	    *softserial_inf=&omap_intr_info[omap_si_to_irq[SI_SOFTSERIAL]],
+	    *l2_inf        =&omap_intr_info[OMAP_INT_L2_IRQ];
+	int i;
+
+	/*
+	 * We just blocked all the interrupts in all the masks.  Now we just
+	 * go through and modify the masks to allow the software interrupts as
+	 * documented in the spl(9) man page.
+	 */
+	for (i = IPL_NONE; i < IPL_SOFT; ++i)
+		level_allow_irq(i, soft_inf);
+	for (i = IPL_NONE; i < IPL_SOFTCLOCK; ++i)
+		level_allow_irq(i, softclock_inf);
+	for (i = IPL_NONE; i < IPL_SOFTNET; ++i)
+		level_allow_irq(i, softnet_inf);
+	for (i = IPL_NONE; i < IPL_SOFTSERIAL; ++i)
+		level_allow_irq(i, softserial_inf);
+
+	/*
+	 * We block level 2 interrupts down in the level 2 controller, so we
+	 * can allow the level 1 interrupt controller to service the level 2
+	 * interrupts at all levels.
+	 */
+	for (i = IPL_NONE; i < IPL_SERIAL; ++i)
+		level_allow_irq(i, l2_inf);
+}
+
+#undef splx
+void
+splx(int ipl)
+{
+	omap_splx(ipl);
+}
+
+#undef _splraise
+int
+_splraise(int ipl)
+{
+	return omap_splraise(ipl);
+}
+
+#undef _spllower
+int
+_spllower(int ipl)
+{
+
+	return omap_spllower(ipl);
+}
+
+#undef _setsoftintr
+void
+_setsoftintr(int si)
+{
+
+	return omap_setsoftintr(si);
+}
+
+void *
+omap_intr_establish(int irqno, int level, const char *name,
+		    int (*func)(void *), void *cookie)
+{
+	const omap_intr_info_t *info;
+	int psw;
+	if (irqno < OMAP_IRQ_MIN || irqno >= OMAP_NIRQ
+	    || irqno == OMAP_INT_L2_IRQ
+	    || omap_intr_info[irqno].trig == INVALID)
+		panic("%s(): bogus irq number %d", __FUNCTION__, irqno);
+
+#ifndef MULTIPLE_HANDLERS_ON_ONE_IRQ
+	if (handler[irqno].func != stray_interrupt)
+		panic("Shared interrupts are not supported (irqno=%d)\n",
+		      irqno);
+#endif
+
+	psw = disable_interrupts(I32_bit);
+
+	/*
+	 * Name the evcnt what they passed us.  Note this will zero the
+	 * count.
+	 */
+	omapintc_set_name(irqno, name, TRUE);
+
+	/* Clear any existing interrupt by writing a zero into its ITR bit. */
+	info = &omap_intr_info[irqno];
+	write_icu(info->bank_base, OMAP_INTB_ITR, ~info->mask);
+
+	handler[irqno].cookie = cookie;
+	handler[irqno].func = func;
+	extirq_level[irqno] = level;
+	omap_update_intr_masks(irqno, level);
+
+	restore_interrupts(psw);
+
+	return (&handler[irqno]);
+}
+
+void
+omap_intr_disestablish(void *v)
+{
+	struct irq_handler *irq_handler = v;
+	int irqno = ((unsigned)v - (unsigned)&handler[0])/sizeof(handler[0]);
+
+	if (irqno < OMAP_IRQ_MIN || irqno >= OMAP_NIRQ
+	    || irqno == OMAP_INT_L2_IRQ
+	    || omap_intr_info[irqno].trig == INVALID)
+		panic("%s(): bogus irq number %d", __FUNCTION__, irqno);
+
+	int psw = disable_interrupts(I32_bit);
+
+	/*
+	 * Put the evcnt name back to our number string.  Note this will zero
+	 * the count.
+	 */
+	omapintc_set_name(irqno, handler[irqno].irq_num_str, TRUE);
+
+	irq_handler->cookie = (void *)(intptr_t) irqno;
+	irq_handler->func = stray_interrupt;
+	extirq_level[irqno] = IPL_SERIAL;
+	omap_update_intr_masks(irqno, IPL_NONE);
+
+	restore_interrupts(psw);
+}
+
+static void
+omapintc_set_name(int irqno, const char *name, int detach_first)
+{
+	const char *group;
+
+	if (irqno < OMAP_INT_L1_NIRQ)
+		group = "omap_intr L1";
+	else
+		group = "omap_intr L2";
+
+	if (detach_first)
+		evcnt_detach(&handler[irqno].ev);
+
+	handler[irqno].name = name;
+
+	evcnt_attach_dynamic(&handler[irqno].ev, EVCNT_TYPE_INTR, NULL,
+			     group, handler[irqno].name);
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_space.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_space.c
@@ -0,0 +1,271 @@
+/*	$NetBSD: $ */
+
+/*
+ * bus_space functions for Texas Instruments OMAP processor.
+ * Based on pxa2x0_space.c which in turn was derived from i80321_space.c.
+ *
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(omap);
+bs_protos(generic);
+bs_protos(generic_armv4);
+bs_protos(bs_notimpl);
+
+struct bus_space omap_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	omap_bs_map,
+	omap_bs_unmap,
+	omap_bs_subregion,
+
+	/* allocation/deallocation */
+	omap_bs_alloc,	/* not implemented */
+	omap_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	omap_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	omap_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_armv4_bs_rm_2,
+	generic_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_armv4_bs_rr_2,
+	generic_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	generic_armv4_bs_wm_2,
+	generic_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	generic_bs_wr_1,
+	generic_armv4_bs_wr_2,
+	generic_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	generic_bs_sr_1,
+	generic_armv4_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	generic_armv4_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+
+int
+omap_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
+	      int flag, bus_space_handle_t *bshp)
+{
+	u_long startpa, endpa, pa;
+	vaddr_t va;
+	pt_entry_t *pte;
+	const struct pmap_devmap	*pd;
+
+	if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
+		/* Device was statically mapped. */
+		*bshp = pd->pd_va + (bpa - pd->pd_pa);
+		return 0;
+	}
+
+	startpa = trunc_page(bpa);
+	endpa = round_page(bpa + size);
+
+	/* XXX use extent manager to check duplicate mapping */
+
+	va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
+	    UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
+	if (! va)
+		return(ENOMEM);
+
+	*bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+	for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
+		if ((flag & BUS_SPACE_MAP_CACHEABLE) == 0) {
+			pte = vtopte(va);
+			*pte &= ~L2_S_CACHE_MASK;
+			PTE_SYNC(pte);
+			/* XXX: pmap_kenter_pa() also does PTE_SYNC(). a bit of
+			 *      waste.
+			 */
+		}
+	}
+	pmap_update(pmap_kernel());
+
+	return(0);
+}
+
+void
+omap_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+	vaddr_t	va;
+	vsize_t	sz;
+
+	if (pmap_devmap_find_va(bsh, size) != NULL) {
+		/* Device was statically mapped; nothing to do. */
+		return;
+	}
+
+	va = trunc_page(bsh);
+	sz = round_page(bsh + size) - va;
+
+	pmap_kremove(va, sz);
+	pmap_update(pmap_kernel());
+	uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
+}
+
+
+int
+omap_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+	*nbshp = bsh + offset;
+	return (0);
+}
+
+void
+omap_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+    bus_size_t len, int flags)
+{
+
+	/* Nothing to do. */
+}
+
+void *
+omap_bs_vaddr(void *t, bus_space_handle_t bsh)
+{
+
+	return ((void *)bsh);
+}
+
+
+int
+omap_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+    bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+    bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+	panic("%s(): not implemented\n", __FUNCTION__);
+}
+
+void
+omap_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+	panic("%s(): not implemented\n", __FUNCTION__);
+}
+
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_mputmr.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_mputmr.c
@@ -0,0 +1,486 @@
+/*	$NetBSD: $	*/
+
+/*
+ * Based on i80321_timer.c and arch/arm/sa11x0/sa11x0_ost.c
+ *
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/device.h>
+
+#include <dev/clock_subr.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_tipb.h>
+
+#include "opt_omap.h"
+
+static int	omapmputmr_match(struct device *, struct cfdata *, void *);
+static void	omapmputmr_attach(struct device *, struct device *, void *);
+
+static int	clockintr(void *);
+static int	statintr(void *);
+void		rtcinit(void);
+
+typedef struct timer_factors {
+	uint32_t ptv;
+	uint32_t reload;
+	uint32_t counts_per_usec;
+} timer_factors;
+static void	calc_timer_factors(int, timer_factors*);
+
+struct omapmputmr_softc {
+	struct device		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	int			sc_intr;
+};
+
+static uint32_t counts_per_usec, counts_per_hz;
+static uint32_t hardref;
+static struct timeval hardtime;
+static struct omapmputmr_softc *clock_sc = NULL;
+static struct omapmputmr_softc *stat_sc = NULL;
+static struct omapmputmr_softc *ref_sc = NULL;
+
+#ifndef STATHZ
+#define STATHZ	64
+#endif
+
+#ifndef OMAP_MPU_TIMER_CLOCK_FREQ
+#error Specify the timer frequency in Hz with the OMAP_MPU_TIMER_CLOCK_FREQ option.
+#endif
+
+/* Encapsulate the device knowledge within this source. */
+/* Register offsets and values */
+#define MPU_CNTL_TIMER	0x00
+#define  MPU_FREE		(1<<6)
+#define  MPU_CLOCK_ENABLE	(1<<5)
+#define  MPU_PTV_SHIFT		2
+#define  MPU_AR			(1<<1)
+#define  MPU_ST			(1<<0)
+#define MPU_LOAD_TIMER	0x04
+#define MPU_READ_TIMER	0x08
+
+CFATTACH_DECL(omapmputmr, sizeof(struct omapmputmr_softc),
+    omapmputmr_match, omapmputmr_attach, NULL, NULL);
+
+static int
+omapmputmr_match(struct device *parent, struct cfdata *match, void *aux)
+{
+	struct tipb_attach_args *tipb = aux;
+
+	if (tipb->tipb_addr == -1 || tipb->tipb_intr == -1)
+	    panic("omapmputmr must have addr and intr specified in config.");
+
+	if (tipb->tipb_size == 0)
+		tipb->tipb_size = 256;	/* Per the OMAP TRM. */
+
+	/* We implicitly trust the config file. */
+	return (1);
+}
+
+void
+omapmputmr_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct omapmputmr_softc *sc = (struct omapmputmr_softc*)self;
+	struct tipb_attach_args *tipb = aux;
+	int ints_per_sec;
+
+	sc->sc_iot = tipb->tipb_iot;
+	sc->sc_intr = tipb->tipb_intr;
+
+	if (bus_space_map(tipb->tipb_iot, tipb->tipb_addr, tipb->tipb_size, 0,
+			 &sc->sc_ioh))
+		panic("%s: Cannot map registers", self->dv_xname);
+
+	switch (self->dv_unit) {
+	case 0:
+		clock_sc = sc;
+		ints_per_sec = hz;
+		break;
+	case 1:
+		stat_sc = sc;
+		ints_per_sec = profhz = stathz = STATHZ;
+		break;
+	case 2:
+		ref_sc = sc;
+		ints_per_sec = hz;	/* Same rate as clock */
+		break;
+	default:
+		ints_per_sec = hz;	/* Better value? */
+		break;
+	}
+
+	aprint_normal(": OMAP MPU Timer\n");
+	aprint_naive("\n");
+
+	/* Stop the timer from counting, but keep the timer module working. */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER,
+			  MPU_CLOCK_ENABLE);
+
+	timer_factors tf;
+	calc_timer_factors(ints_per_sec, &tf);
+
+	switch (self->dv_unit) {
+	case 0:
+		counts_per_hz = tf.reload + 1;
+		counts_per_usec = tf.counts_per_usec;
+		break;
+	case 2:
+
+		/*
+		 * The microtime reference clock for all practical purposes
+		 * just wraps around as an unsigned int.
+		 */
+
+		tf.reload = 0xffffffff;
+		break;
+
+	default:
+		break;
+	}
+
+	/* Set the reload value. */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_LOAD_TIMER, tf.reload);
+	/* Set the PTV and the other required bits and pieces. */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MPU_CNTL_TIMER,
+			  ( MPU_CLOCK_ENABLE
+			    | (tf.ptv << MPU_PTV_SHIFT)
+			    | MPU_AR
+			    | MPU_ST));
+	/* The clock is now running, but is not generating interrupts. */
+}
+
+static int
+clockintr(void *arg)
+{
+	struct clockframe *frame = arg;
+	unsigned int newref;
+	int ticks, i, oldirqstate;
+
+	oldirqstate = disable_interrupts(I32_bit);
+	hardtime = time;
+	newref = bus_space_read_4(ref_sc->sc_iot, ref_sc->sc_ioh,
+				  MPU_READ_TIMER);
+	ticks = hardref ? (hardref - newref) / counts_per_hz : 1;
+	hardtime.tv_usec += (hardref - newref) / counts_per_usec;
+	hardref = newref;
+	restore_interrupts(oldirqstate);
+
+	if (ticks == 0)
+		ticks = 1;
+
+#ifdef DEBUG
+	if (ticks > 1)
+		printf("Missed %d ticks.\n", ticks-1);
+#endif
+
+
+	for (i = 0; i < ticks; i++)
+		hardclock(frame);
+
+	if (ticks > 1) {
+		newref = bus_space_read_4(ref_sc->sc_iot, ref_sc->sc_ioh,
+					  MPU_READ_TIMER);
+
+		if ((hardref - newref) / counts_per_hz)
+			hardclock(frame);
+	}
+
+	return(1);
+}
+
+static int
+statintr(void *arg)
+{
+	struct clockframe *frame = arg;
+
+	statclock(frame);
+
+	return(1);
+}
+
+
+void
+setstatclockrate(int schz)
+{
+	/* Stop the timer from counting, but keep the timer module working. */
+	bus_space_write_4(stat_sc->sc_iot, stat_sc->sc_ioh, MPU_CNTL_TIMER,
+			  MPU_CLOCK_ENABLE);
+
+	timer_factors tf;
+	calc_timer_factors(schz, &tf);
+
+	/* Set the reload value. */
+	bus_space_write_4(stat_sc->sc_iot, stat_sc->sc_ioh, MPU_LOAD_TIMER,
+			  tf.reload);
+	/* Set the PTV and the other required bits and pieces. */
+	bus_space_write_4(stat_sc->sc_iot, stat_sc->sc_ioh, MPU_CNTL_TIMER,
+			  ( MPU_CLOCK_ENABLE
+			    | (tf.ptv << MPU_PTV_SHIFT)
+			    | MPU_AR
+			    | MPU_ST));
+}
+
+void
+cpu_initclocks(void)
+{
+	if (clock_sc == NULL)
+		panic("Clock timer was not configured.");
+	if (stat_sc == NULL)
+		panic("Statistics timer was not configured.");
+	if (ref_sc == NULL)
+		panic("Microtime reference timer was not configured.");
+
+	/*
+	 * We already have the timers running, but not generating interrupts.
+	 * In addition, we've set stathz and profhz.
+	 */
+	printf("clock: hz=%d stathz=%d\n", hz, stathz);
+
+	/*
+	 * The "cookie" parameter must be zero to pass the interrupt frame
+	 * through to hardclock() and statclock().
+	 */
+
+	omap_intr_establish(clock_sc->sc_intr, IPL_CLOCK,
+			    clock_sc->sc_dev.dv_xname, clockintr, 0);
+	omap_intr_establish(stat_sc->sc_intr, IPL_STATCLOCK,
+			    stat_sc->sc_dev.dv_xname, statintr, 0);
+}
+
+void
+microtime(struct timeval *tvp)
+{
+	u_int oldirqstate;
+	uint32_t ref, baseref;
+	static struct timeval lasttime;
+	static uint32_t lastref;
+
+	if (clock_sc == NULL) {
+		tvp->tv_sec = 0;
+		tvp->tv_usec = 0;
+		return;
+	}
+
+	oldirqstate = disable_interrupts(I32_bit);
+	ref = bus_space_read_4(ref_sc->sc_iot, ref_sc->sc_ioh,
+			       MPU_READ_TIMER);
+
+	*tvp = hardtime;
+	baseref = hardref;
+
+	/*
+	 * If time was just jumped forward and hardtime hasn't caught up
+	 * then just use time.
+	 */
+
+	if (time.tv_sec - hardtime.tv_sec > 1)
+		*tvp = time;
+
+	if (tvp->tv_sec < lasttime.tv_sec ||
+	    (tvp->tv_sec == lasttime.tv_sec &&
+	     tvp->tv_usec < lasttime.tv_usec)) {
+		*tvp = lasttime;
+		baseref = lastref;
+
+	} else {
+		lasttime = *tvp;
+		lastref = ref;
+	}
+
+	restore_interrupts(oldirqstate);
+
+	/* Prior to the first hardclock completion we don't have a
+	   microtimer reference. */
+
+	if (baseref)
+		tvp->tv_usec += (baseref - ref) / counts_per_usec;
+
+	/* Make sure microseconds doesn't overflow. */
+	while (tvp->tv_usec >= 1000000) {
+		tvp->tv_usec -= 1000000;
+		tvp->tv_sec++;
+	}
+}
+
+void
+delay(u_int n)
+{
+	uint32_t cur, last, delta, usecs;
+
+	if (clock_sc == NULL)
+		panic("The timer must be initialized sooner.");
+
+	/*
+	 * This works by polling the timer and counting the
+	 * number of microseconds that go by.
+	 */
+	last = bus_space_read_4(clock_sc->sc_iot, clock_sc->sc_ioh,
+				MPU_READ_TIMER);
+	delta = usecs = 0;
+
+	while (n > usecs) {
+		cur = bus_space_read_4(clock_sc->sc_iot, clock_sc->sc_ioh,
+					MPU_READ_TIMER);
+
+		/* Check to see if the timer has wrapped around. */
+		if (last < cur)
+			delta += (last + (counts_per_hz - cur));
+		else
+			delta += (last - cur);
+
+		last = cur;
+
+		if (delta >= counts_per_usec) {
+			usecs += delta / counts_per_usec;
+			delta %= counts_per_usec;
+		}
+	}
+}
+
+static void
+calc_timer_factors(int ints_per_sec, timer_factors *tf)
+{
+	/*
+	 * From the OMAP Technical Reference Manual:
+	 *  T(MPU_Interrupt) = T(MPU_ref_clk) * (MPU_LOAD_TIMER+1) * 2**(PTV+1)
+	 *
+	 * T(MPU_ref_clk) is 1/OMAP_MPU_TIMER_CLOCK_FREQ and we want
+	 * T(MPU_Interrupt) to be 1/ints_per_sec.  Rewriting the equation:
+	 *
+	 *                    1         (MPU_LOAD_TIMER+1) * 2**(PTV+1)
+	 *               ------------ = -------------------------------
+	 *               ints_per_sec      OMAP_MPU_TIMER_CLOCK_FREQ
+	 *
+	 * or
+	 *
+	 *    OMAP_MPU_TIMER_CLOCK_FREQ
+	 *    ------------------------- = (MPU_LOAD_TIMER+1) * 2**(PTV+1)
+	 *           ints_per_sec
+	 *
+	 * or
+	 *
+	 *    OMAP_MPU_TIMER_CLOCK_FREQ
+	 *    ------------------------- = (MPU_LOAD_TIMER+1)
+	 *    ints_per_sec * 2**(PTV+1)
+	 *
+	 *
+	 * To save that last smidgen of power, find the largest prescaler that
+	 * will give us a reload value that doesn't have any error.  However,
+	 * to keep delay() accurate, it is desireable to have the number of
+	 * counts per us be non-fractional.
+	 *
+	 * us_incs = OMAP_MPU_TIMER_CLOCK_FREQ / 2**(PTV+1) / 1,000,000
+	 */
+
+	/* The PTV can range from 7 to 0. */
+	tf->ptv = 7;
+	for (;;) {
+		static const uint32_t us_per_sec = 1000000;
+		uint32_t ptv_power = 1 << (tf->ptv + 1);
+		uint32_t count_freq = OMAP_MPU_TIMER_CLOCK_FREQ / ptv_power;
+
+		tf->reload = count_freq / ints_per_sec;
+		tf->counts_per_usec = count_freq / us_per_sec;
+
+		if ((tf->reload * ptv_power * ints_per_sec
+		     == OMAP_MPU_TIMER_CLOCK_FREQ)
+		    && (tf->counts_per_usec * ptv_power * us_per_sec
+			== OMAP_MPU_TIMER_CLOCK_FREQ))
+		{	/* Exact match.  Life is good. */
+			/* Currently reload is MPU_LOAD_TIMER+1.  Fix it. */
+			tf->reload--;
+			return;
+		}
+		if (tf->ptv == 0) {
+			/*
+			 * Not exact, but we're out of options.  Leave the
+			 * reload at being one too large and bump the counts
+			 * per microsecond up one to make sure that we run a
+			 * bit slow rather than too fast.
+			 */
+			tf->counts_per_usec++;
+			return;
+		}
+		tf->ptv--;
+	}
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_a2x_io.S
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_a2x_io.S
@@ -0,0 +1,103 @@
+/*	$NetBSD: $ */
+
+/*
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * There are simple bus space functions for IO registers mapped at
+ * 32-bit aligned positions.  offset is multiplied by 2.
+ */
+
+#include <machine/asm.h>
+
+/*
+ * bus_space I/O functions with offset*2
+ */
+
+/*
+ * read single
+ */
+
+ENTRY(a2x_bs_r_1)
+	ldrb	r0, [r1, r2, LSL #1]
+	mov	pc, lr
+
+ENTRY(a2x_bs_r_2)
+	mov	r2, r2, LSL #1
+	ldrh	r0, [r1, r2]
+	mov	pc, lr
+
+ENTRY(a2x_bs_r_4)
+	ldr	r0, [r1, r2, LSL #1]
+	mov	pc, lr
+
+/*
+ * write single
+ */
+
+ENTRY(a2x_bs_w_1)
+	strb	r3, [r1, r2, LSL #1]
+	mov	pc, lr
+
+ENTRY(a2x_bs_w_2)
+	mov	r2, r2, LSL #1
+	strh	r3, [r1, r2]
+	mov	pc, lr
+
+ENTRY(a2x_bs_w_4)
+	str	r3, [r1, r2, LSL #1]
+	mov	pc, lr
+
+/*
+ * read multiple
+ */
+ENTRY(a2x_bs_rm_1)
+	mov r2, r2, LSL #1
+	b generic_bs_rm_1
+
+ENTRY(a2x_bs_rm_2)
+	mov r2, r2, LSL #1
+	b generic_armv4_bs_rm_2
+
+
+
+/*
+ * write multiple
+ */
+ENTRY(a2x_bs_wm_1)
+	mov r2, r2, LSL #1
+	b generic_bs_wm_1
+
+ENTRY(a2x_bs_wm_2)
+	mov r2, r2, LSL #1
+	b generic_armv4_bs_wm_2
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_a2x_space.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_a2x_space.c
@@ -0,0 +1,136 @@
+/*	$NetBSD: $ */
+
+/*
+ * Based on arch/arm/xscale/pxa2x0_a4x_space.c
+ *
+ * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Bus space tag for 8/16-bit devices on 32-bit bus.
+ * all registers are located at the address of multiple of 2.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(omap);
+bs_protos(a2x);
+bs_protos(bs_notimpl);
+
+struct bus_space omap_a2x_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	omap_bs_map,
+	omap_bs_unmap,
+	omap_bs_subregion,
+
+	/* allocation/deallocation */
+	omap_bs_alloc,	/* not implemented */
+	omap_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	omap_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	omap_bs_barrier,
+
+	/* read (single) */
+	a2x_bs_r_1,
+	a2x_bs_r_2,
+	a2x_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	a2x_bs_rm_1,
+	a2x_bs_rm_2,
+	bs_notimpl_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	bs_notimpl_bs_rr_1,
+	bs_notimpl_bs_rr_2,
+	bs_notimpl_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	a2x_bs_w_1,
+	a2x_bs_w_2,
+	a2x_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	a2x_bs_wm_1,
+	a2x_bs_wm_2,
+	bs_notimpl_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	bs_notimpl_bs_wr_1,
+	bs_notimpl_bs_wr_2,
+	bs_notimpl_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	bs_notimpl_bs_sr_1,
+	bs_notimpl_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	bs_notimpl_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+
+
+
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_emifs.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_emifs.c
@@ -0,0 +1,433 @@
+/*	$NetBSD: $ */
+
+
+/*
+ * Autoconfiguration support for the Texas Instruments OMAP EMIFS bus.
+ * Based on arm/xscale/pxa2x0.c which in turn was derived
+ * from arm/sa11x0/sa11x0.c
+ *
+ * Copyright (c) 2002, 2005  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Copyright (c) 1999
+ *         Shin Takemura and PocketBSD Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the PocketBSD project
+ *	and its contributors.
+ * 4. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 1997,1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include "locators.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+
+#include <arm/cpufunc.h>
+#include <arm/mainbus/mainbus.h>
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_emifs.h>
+
+struct emifs_softc {
+	struct device		sc_dev;
+	bus_dma_tag_t		sc_dmac;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+};
+
+enum which_clock { TC_CLK, REF_CLK };
+enum which_reg { CCS, ACS };
+typedef struct timing_parm_info {
+	const char	*name;			/* name of parm */
+	int		cf_ndx;			/* Index to get parm */
+	enum		which_clock clk;	/* TC_CLK or REF_CLK */
+	enum		which_reg reg;		/* CCS or ACS? */
+	u_int		shift;			/* Field's register position */
+	u_int		adder;			/* Number of cycles to add */
+	u_int		max;			/* Maximum field value */
+} timing_parm_info;
+
+/* prototypes */
+static int	emifs_match(struct device *, struct cfdata *, void *);
+static void	emifs_attach(struct device *, struct device *, void *);
+static u_int	emifs_cvt_nsec(const timing_parm_info *, u_int, int);
+static void	emifs_set_timing(struct emifs_softc *, struct cfdata *);
+static int 	emifs_search(struct device *, struct cfdata *,
+			     const int *, void *);
+static int	emifs_print(void *, const char *);
+
+#ifndef OMAP_TC_CLOCK_FREQ
+#error Specify the TC clock frequency in Hz with the OMAP_TC_CLOCK_FREQ option.
+#endif
+
+/* Encapsulate the device knowledge within this source. */
+/* Register offsets, values and information needed to set them. */
+#define EMIFS_CCS(cs)	(0x10+((cs)*4))	/* chip-select config */
+#define EMIFS_ACS(cs)	(0x50+((cs)*4))	/* advanced chip-select config */
+#define  EMIFS_ACS_BTMODE	(1<<9)
+#define EMIFS_SIZE			256	/* per TRM */
+
+static const timing_parm_info timing_parms[] = {
+	{ "rdwst",   EMIFSCF_RDWST,   REF_CLK, CCS,  4, 2, 0xF },
+	{ "oesetup", EMIFSCF_OESETUP, REF_CLK, ACS,  0, 0, 0xF },
+	{ "oehold",  EMIFSCF_OEHOLD,  REF_CLK, ACS,  4, 0, 0xF },
+	{ "wrwst",   EMIFSCF_WRWST,   REF_CLK, CCS,  8, 1, 0xF },
+	{ "welen",   EMIFSCF_WELEN,   REF_CLK, CCS, 12, 1, 0xF },
+	{ "advhold", EMIFSCF_ADVHOLD, REF_CLK, ACS,  8, 1, 0x1 },
+	{ "btwst",   EMIFSCF_BTWST,   TC_CLK,  CCS, 23, 1, 0xF }
+};
+
+/* attach structures */
+CFATTACH_DECL(emifs, sizeof(struct emifs_softc),
+    emifs_match, emifs_attach, NULL, NULL);
+
+static int emifs_attached;
+
+static int
+emifs_match(struct device *parent, struct cfdata *match, void *aux)
+{
+	if (emifs_attached)
+		return 0;
+	return 1;
+}
+
+static void
+emifs_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct emifs_softc *sc = (struct emifs_softc *)self;
+	struct mainbus_attach_args *mainbus = aux;
+
+	/*
+	 * mainbus->mb_iot always multiplies the offset by 4 and doesn't seem
+	 * to be widely used, so I'm just going to use the omap bus.
+	 */
+	if (mainbus->mb_iobase != -1) {
+		/*
+		 * The address is only needed for modifying the timings, so
+		 * don't make it mandatory.  We'll check to see if it was set
+		 * when (and if) it is needed.
+		 */
+		sc->sc_iot = &omap_bs_tag;
+		if (bus_space_map(sc->sc_iot,
+				  mainbus->mb_iobase, EMIFS_SIZE,
+				  0, &sc->sc_ioh))
+			panic("%s: Cannot map registers", self->dv_xname);
+	} else
+		sc->sc_iot = NULL;
+
+	emifs_attached = 1;
+
+#if NOMAPDMAC > 0
+#error DMA not implemented
+	sc->sc_dmac = &omap_bus_dma_tag;
+#else
+	sc->sc_dmac = NULL;
+#endif
+
+	aprint_normal(": Extended Memory Interface Slow\n");
+	aprint_naive("\n");
+
+	/*
+	 * Attach all our devices
+	 */
+	config_search_ia(emifs_search, self, "emifs", NULL);
+}
+
+static const u_int ns_per_sec = 1000000000;
+
+static u_int
+emifs_cvt_nsec(const timing_parm_info *tp, u_int source_freq, int nsec)
+{
+	u_int desired_freq, clocks, rval;
+
+	/*
+	 * It is easier to work with a frequency in Hz, instead of a
+	 * period in nanoseconds.
+	 */
+	desired_freq = ns_per_sec / nsec;
+
+	/*
+	 * Then we can just divide the source frequency by the desired
+	 * frequency to get the number of clocks.  If it doesn't divide
+	 * evenly, round up to make sure the period is long enough.
+	 */
+	clocks = source_freq / desired_freq;
+	if ((clocks * desired_freq) != source_freq)
+		clocks++;
+
+	/* Adjust for the number of cycles that are added. */
+	rval = clocks - tp->adder;
+
+	/* Limit to maximum */
+	if (rval > tp->max) {
+		aprint_error("EMIFS: %s: %d ns is too large.\n",
+			     tp->name, nsec);
+		rval = tp->max;
+	}
+
+	return rval;
+}
+
+static void
+emifs_set_timing(struct emifs_softc *sc, struct cfdata *cf)
+{
+	static const u_int tc_freq = OMAP_TC_CLOCK_FREQ;
+	/* We force REF to be the same frequency as TC. */
+	static const u_int ref_freq = tc_freq;
+
+	int cs, i;
+	uint32_t ccs, acs;
+
+	/*
+	 * Ensure we have what everything we need to set the EMIFS bus
+	 * timing parameters.
+	 */
+	cs = cf->cf_loc[EMIFSCF_CS];
+	if (cs < 0 || cs > 3)
+		panic("cs parameter must be in the range of 0 to 3.");
+	if (sc->sc_iot == NULL)
+		panic("Parent emifs device must have base specified.");
+
+	ccs = 0;
+	acs = 0;
+	switch (cf->cf_loc[EMIFSCF_BTMODE]) {
+	case -1:
+	case 0:
+		break;
+	case 1:
+		acs = EMIFS_ACS_BTMODE;
+		break;
+	default:
+		panic("btmode must be 0, 1 or not given.");
+	}
+
+	aprint_verbose("EMIFS:  TC_CK period: %u ns\n", ns_per_sec / tc_freq);
+	aprint_verbose("EMIFS: REF_CK period: %u ns\n", ns_per_sec / ref_freq);
+
+	for (i = 0; i < __arraycount(timing_parms); i++) {
+		const timing_parm_info *tp;
+		int nsec;
+		u_int source_freq, field_val;
+
+		tp = &timing_parms[i];
+		nsec = cf->cf_loc[tp->cf_ndx];
+
+		/* Blow up on completely wrong parameters. */
+		if (nsec < 0 || nsec > OMAP_TC_CLOCK_FREQ)
+			panic("Invalid %s period of %d nsec.", tp->name, nsec);
+
+		if (tp->clk == REF_CLK)
+			source_freq = ref_freq;
+		else
+			source_freq = tc_freq;
+
+		if (nsec == 0)
+			/*
+			 * Handle the zero case separately because: 1) it
+			 * avoids a divide by zero case, 2) we already know
+			 * the answer is zero, and 3) we know the field is
+			 * already zeroed.
+			 */
+			field_val = 0;
+		else {
+			field_val = emifs_cvt_nsec(tp, source_freq, nsec);
+
+			if (tp->reg == CCS)
+				ccs |= (field_val << tp->shift);
+			else
+				acs |= (field_val << tp->shift);
+		}
+
+		/*
+		 * Tell them what they got.  The ">> 5"'s are to prevent
+		 * overflow.  We know ns_per_sec fits in a word, and we know
+		 * that (field_val + tp->addr) is less than five bits.  If we
+		 * shift the numerator and denominator the same amount, we'll
+		 * get the same answer, but without overflow.
+		 */
+		aprint_verbose("EMIFS: %8s: Requested %4u ns.  Got %4u ns.\n",
+			       tp->name, nsec,
+			       ((field_val + tp->adder) * (ns_per_sec >> 5)
+				/ (source_freq >> 5)));
+	}
+
+	/* Now tell the hardware what we figured out. */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMIFS_CCS(cs), ccs);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMIFS_ACS(cs), acs);
+}
+
+static int
+emifs_search(struct device *parent, struct cfdata *cf,
+	     const int *ldesc, void *aux)
+{
+	struct emifs_softc *sc = (struct emifs_softc *)parent;
+	struct emifs_attach_args aa;
+
+	/* Set up the attach args. */
+	if (cf->cf_loc[EMIFSCF_NOBYTEACC] == 1) {
+		if (cf->cf_loc[EMIFSCF_MULT] == 1)
+			aa.emifs_iot = &nobyteacc_bs_tag;
+		else
+			panic("nobyteacc specified for device with non-byte multiplier\n");
+	} else {
+		switch (cf->cf_loc[EMIFSCF_MULT]) {
+		case 1:
+			aa.emifs_iot = &omap_bs_tag;
+			break;
+		case 2:
+			aa.emifs_iot = &omap_a2x_bs_tag;
+			break;
+		case 4:
+			aa.emifs_iot = &omap_a4x_bs_tag;
+			break;
+		default:
+			panic("Unsupported EMIFS multiplier.");
+			break;
+		}
+	}
+
+	aa.emifs_dmac = sc->sc_dmac;
+	aa.emifs_addr = cf->cf_loc[EMIFSCF_ADDR];
+	aa.emifs_size = cf->cf_loc[EMIFSCF_SIZE];
+	aa.emifs_intr = cf->cf_loc[EMIFSCF_INTR];
+
+	/* Chip-select specified? */
+	if (cf->cf_loc[EMIFSCF_CS] != -1)
+		emifs_set_timing(sc, cf);
+
+	if (config_match(parent, cf, &aa))
+		config_attach(parent, cf, &aa, emifs_print);
+
+	return 0;
+}
+
+static int
+emifs_print(void *aux, const char *name)
+{
+	struct emifs_attach_args *sa = (struct emifs_attach_args*)aux;
+
+	if (sa->emifs_addr != EMIFSCF_ADDR_DEFAULT) {
+		aprint_normal(" addr 0x%08lx", sa->emifs_addr);
+		if (sa->emifs_size > EMIFSCF_SIZE_DEFAULT)
+			aprint_normal("-0x%08lx", sa->emifs_addr + sa->emifs_size-1);
+	}
+	if (sa->emifs_intr != EMIFSCF_INTR_DEFAULT)
+		aprint_normal(" intr %d", sa->emifs_intr);
+
+	return (UNCONF);
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_emifs.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_emifs.h
@@ -0,0 +1,45 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_OMAP_OMAP_EMIFS_H_
+#define _ARM_OMAP_OMAP_EMIFS_H_
+
+/* Extended Memory Interface Slow */
+
+struct emifs_attach_args {
+	bus_space_tag_t	emifs_iot;	/* Bus tag */
+	bus_addr_t	emifs_addr;	/* Address */
+	bus_size_t	emifs_size;	/* Size of peripheral address space */
+	int		emifs_intr;	/* IRQ number */
+	bus_dma_tag_t	emifs_dmac;	/* DMA channel */
+	unsigned int	emifs_mult;	/* Offset multiplier */
+};
+
+extern struct bus_space omap_bs_tag;
+extern struct arm32_bus_dma_tag omap_bus_dma_tag;
+extern struct bus_space omap_a4x_bs_tag;
+extern struct bus_space omap_a2x_bs_tag;
+extern struct bus_space nobyteacc_bs_tag;
+
+#endif /* _ARM_OMAP_OMAP_EMIFS_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_com.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_com.h
@@ -0,0 +1,136 @@
+/*	$NetBSD: $	*/
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_OMAP_OMAP_COM_H_
+#define _ARM_OMAP_OMAP_COM_H_
+
+/*
+ * Minimal defines for the bits and bytes we need.  We need these definitions
+ * in both omap_com.c and the machdep startup file to get the console and kgdb
+ * ports initialized.
+ */
+#define OMAP_COM_SIZE			1024 	/* Per the OMAP TRM. */
+
+/*
+ * Registers 0x00 to 0x07 are pretty much 16550 compatible.  Let the com
+ * driver handle them.
+ */
+
+/* Mode Definition Register 1 */
+#define OMAP_COM_MDR1			0x08
+/* There are IrDA specific bits as well. */
+#define  OMAP_COM_MDR1_MODE_MASK		(7<<0)
+#define  OMAP_COM_MDR1_MODE_UART_16X		(0<<0)
+#define  OMAP_COM_MDR1_MODE_SIR			(1<<0)
+#define  OMAP_COM_MDR1_MODE_UART_16X_AUTOBAUD	(2<<0)
+#define  OMAP_COM_MDR1_MODE_UART_13X		(3<<0)
+#define  OMAP_COM_MDR1_MODE_MIR			(4<<0)
+#define  OMAP_COM_MDR1_MODE_FIR			(5<<0)
+#define  OMAP_COM_MDR1_MODE_DISABLE		(7<<0)
+
+/* Mode Definition Register 2 (0x09) is for IrDA */
+
+/* Status FIFO Line Status and Transmit Frame Length Low (0x0A) are for IrDA */
+/* Resume and Transmit Frame Length High (0x0B) are for IrDA */
+/* Status FIFO Low and Received Frame Length Low (0x0C) are for IrDA */
+/* Status FIFO High and Received Frame Length High (0x0D) are for IrDA */
+/* BOF Control Register (0x0E) is for IrDA */
+
+/* UART Autobauding Status Register */
+#define OMAP_COM_UASR			0x0E
+#define  OMAP_COM_UASR_PARITY_MASK		(3<<6)
+#define   OMAP_COM_UASR_PARITY_NONE		(0<<6)
+#define   OMAP_COM_UASR_PARITY_SPACE		(1<<6)
+#define   OMAP_COM_UASR_PARITY_EVEN		(2<<6)
+#define   OMAP_COM_UASR_PARITY_ODD		(3<<6)
+#define  OMAP_COM_UASR_BIT_BY_CHAR_MASK		(1<<5)
+#define   OMAP_COM_UASR_BIT_BY_CHAR_7		(0<<5)
+#define   OMAP_COM_UASR_BIT_BY_CHAR_8		(1<<5)
+#define  OMAP_COM_UASR_SPEED_MASK		(0x1F<<0)
+#define   OMAP_COM_UASR_SPEED_NONE		(0x00<<0)
+#define   OMAP_COM_UASR_SPEED_115200		(0x01<<0)
+#define   OMAP_COM_UASR_SPEED_57600		(0x02<<0)
+#define   OMAP_COM_UASR_SPEED_38400		(0x03<<0)
+#define   OMAP_COM_UASR_SPEED_28800		(0x04<<0)
+#define   OMAP_COM_UASR_SPEED_19200		(0x05<<0)
+#define   OMAP_COM_UASR_SPEED_14400		(0x06<<0)
+#define   OMAP_COM_UASR_SPEED_9600		(0x07<<0)
+#define   OMAP_COM_UASR_SPEED_4800		(0x08<<0)
+#define   OMAP_COM_UASR_SPEED_2400		(0x09<<0)
+#define   OMAP_COM_UASR_SPEED_1200		(0x0A<<0)
+
+/* Auxiliary Control Register (0x0F) is for IrDA */
+
+/* Supplementary Control Register */
+#define OMAP_COM_SCR			0x10
+#define  OMAP_COM_SCR_RX_TRIG_GRANU1		(1<<7)
+#define  OMAP_COM_SCR_TX_TRIG_GRANU1		(1<<6)
+#define  OMAP_COM_SCR_DSR_IT			(1<<5)
+#define  OMAP_COM_SCR_RX_CTS_DSR_WAKE_UP_ENABLE	(1<<4)
+#define  OMAP_COM_SCR_TX_EMPTY_CTL_IT		(1<<3)
+#define  OMAP_COM_SCR_DMA_MODE_2_0		(0<<1)
+#define  OMAP_COM_SCR_DMA_MODE_2_1		(1<<1)
+#define  OMAP_COM_SCR_DMA_MODE_2_2		(2<<1)
+#define  OMAP_COM_SCR_DMA_MODE_2_3		(3<<1)
+#define  OMAP_COM_SCR_DMA_MODE_CTL		(1<<0)
+
+/* Supplementary Status Register */
+#define OMAP_COM_SSR			0x11
+#define  OMAP_COM_SSR_RX_CTS_DSR_WAKE_UP_STS	(1<<1)
+#define  OMAP_COM_SSR_TX_FIFO_FULL		(1<<0)
+
+/* BOF Length Register (0x12) is for IrDA */
+
+/* Module Version Register */
+#define OMAP_COM_MVR			0x14
+#define  OMAP_COM_MVR_MAJOR(r)			((r>>4) & 0x0F)
+#define  OMAP_COM_MVR_MINOR(r)			((r>>0) & 0x0F)
+
+/* System Configuration Register */
+#define OMAP_COM_SYSC			0x15
+#define  OMAP_COM_SYSC_FORCE_IDLE		(0<<3)
+#define  OMAP_COM_SYSC_NO_IDLE			(1<<3)
+#define  OMAP_COM_SYSC_SMART_IDLE		(2<<3)
+#define  OMAP_COM_SYSC_ENA_WAKE_UP		(1<<2)
+#define  OMAP_COM_SYSC_SOFT_RESET		(1<<1)
+#define  OMAP_COM_SYSC_AUTOIDLE			(1<<0)
+
+/* System Status Register */
+#define OMAP_COM_SYSS			0x16
+#define  OMAP_COM_SYSS_RESET_DONE		(1<<0)
+
+/* Wake-Up Enable Register */
+#define OMAP_COM_WER			0x17
+#define  OMAP_COM_WER_LINE_STATUS		(1<<6)
+#define  OMAP_COM_WER_RHR			(1<<5)
+#define  OMAP_COM_WER_RX			(1<<4)
+#define  OMAP_COM_WER_DCD			(1<<3)
+#define  OMAP_COM_WER_RI			(1<<2)
+#define  OMAP_COM_WER_DSR			(1<<1)
+#define  OMAP_COM_WER_CTS			(1<<0)
+
+/* Base frequency */
+#define OMAP_COM_FREQ	48000000L
+
+#endif /* _ARM_OMAP_OMAP_COM_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_ocp.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_ocp.c
@@ -0,0 +1,240 @@
+/*	$NetBSD: $ */
+
+/*
+ * Autoconfiguration support for the Texas Instruments OMAP OCP bus.
+ * Based on arm/xscale/pxa2x0.c which in turn was derived
+ * from arm/sa11x0/sa11x0.c
+ *
+ * Copyright (c) 2002, 2005  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Copyright (c) 1999
+ *         Shin Takemura and PocketBSD Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the PocketBSD project
+ *	and its contributors.
+ * 4. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 1997,1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Paul Kranenburg.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include "locators.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+
+#include <arm/cpufunc.h>
+#include <arm/mainbus/mainbus.h>
+#include <arm/omap/omap_reg.h>
+#include <arm/omap/omap_ocp.h>
+
+struct ocp_softc {
+	struct device sc_dev;
+	bus_dma_tag_t sc_dmac;
+};
+
+/* prototypes */
+static int	ocp_match(struct device *, struct cfdata *, void *);
+static void	ocp_attach(struct device *, struct device *, void *);
+static int 	ocp_search(struct device *, struct cfdata *,
+			     const int *, void *);
+static int	ocp_print(void *, const char *);
+
+/* attach structures */
+CFATTACH_DECL(ocp, sizeof(struct ocp_softc),
+    ocp_match, ocp_attach, NULL, NULL);
+
+static int ocp_attached;
+
+static int
+ocp_match(struct device *parent, struct cfdata *match, void *aux)
+{
+	if (ocp_attached)
+		return 0;
+	return 1;
+}
+
+static void
+ocp_attach(struct device *parent, struct device *self, void *aux)
+{
+	struct ocp_softc *sc = (struct ocp_softc *)self;
+
+	ocp_attached = 1;
+
+#if NOMAPDMAC > 0
+#error DMA not implemented
+	sc->sc_dmac = &omap_bus_dma_tag;
+#else
+	sc->sc_dmac = NULL;
+#endif
+
+	aprint_normal(": OCP Bus\n");
+	aprint_naive("\n");
+
+	/*
+	 * Attach all our devices
+	 */
+	config_search_ia(ocp_search, self, "ocp", NULL);
+}
+
+static int
+ocp_search(struct device *parent, struct cfdata *cf,
+	     const int *ldesc, void *aux)
+{
+	struct ocp_softc *sc = (struct ocp_softc *)parent;
+	struct ocp_attach_args aa;
+
+	switch (cf->cf_loc[OCPCF_MULT]) {
+	case 1:
+		aa.ocp_iot = &omap_bs_tag;
+		break;
+	case 2:
+		aa.ocp_iot = &omap_a2x_bs_tag;
+		break;
+	case 4:
+		aa.ocp_iot = &omap_a4x_bs_tag;
+		break;
+	default:
+		panic("Unsupported OCP multiplier.");
+		break;
+	}
+	aa.ocp_dmac = sc->sc_dmac;
+	aa.ocp_addr = cf->cf_loc[OCPCF_ADDR];
+	aa.ocp_size = cf->cf_loc[OCPCF_SIZE];
+	aa.ocp_intr = cf->cf_loc[OCPCF_INTR];
+
+	if (config_match(parent, cf, &aa))
+		config_attach(parent, cf, &aa, ocp_print);
+
+	return 0;
+}
+
+static int
+ocp_print(void *aux, const char *name)
+{
+	struct ocp_attach_args *sa = (struct ocp_attach_args*)aux;
+
+	if (sa->ocp_addr != OCPCF_ADDR_DEFAULT) {
+		aprint_normal(" addr 0x%08lx", sa->ocp_addr);
+		if (sa->ocp_size > OCPCF_SIZE_DEFAULT)
+			aprint_normal("-0x%08lx", sa->ocp_addr + sa->ocp_size-1);
+	}
+	if (sa->ocp_intr != OCPCF_INTR_DEFAULT)
+		aprint_normal(" intr %d", sa->ocp_intr);
+
+	return (UNCONF);
+}
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_ocp.h
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_ocp.h
@@ -0,0 +1,44 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_OMAP_OMAP_OCP_H_
+#define _ARM_OMAP_OMAP_OCP_H_
+
+/* Texas Instruments OCP Bus */
+
+struct ocp_attach_args {
+	bus_space_tag_t	ocp_iot;	/* Bus tag */
+	bus_addr_t	ocp_addr;	/* Address */
+	bus_size_t	ocp_size;	/* Size of peripheral address space */
+	int		ocp_intr;	/* IRQ number */
+	bus_dma_tag_t	ocp_dmac;	/* DMA channel */
+	unsigned int	ocp_mult;	/* Offset multiplier */
+};
+
+extern struct bus_space omap_bs_tag;
+extern struct arm32_bus_dma_tag omap_bus_dma_tag;
+extern struct bus_space omap_a4x_bs_tag;
+extern struct bus_space omap_a2x_bs_tag;
+
+#endif /* _ARM_OMAP_OMAP_OCP_H_ */
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_start.S
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_start.S
@@ -0,0 +1,220 @@
+/*	$NetBSD: $ */
+
+/*
+ * Machine dependant startup code for OMAP boards.
+ * Based on lubbock_start.S and tsarm_start.S
+ *
+ * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Genetec Corporation may not be used to endorse or
+ *    promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2003
+ *	Ichiro FUKUHARA <ichiro@ichiro.org>.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Ichiro FUKUHARA.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "assym.h"
+
+#include <machine/asm.h>
+#include <arm/armreg.h>
+#undef DOMAIN_CLIENT	/* assym.h defines as 1, but pte.h defines as 0x01 */
+#include <arm/arm32/pmap.h>
+#include <arm/omap/omap_reg.h>
+
+/*
+ * Kernel start routine for OMAP boards.
+ * At this point, this code has been loaded into the very beginning of SDRAM
+ * and the MMU is off, which implies the data cache is off.
+ */
+	.section .start,"ax",%progbits
+
+	.global	_C_LABEL(omap_start)
+_C_LABEL(omap_start):
+	/* Move into supervisor mode and disable IRQs/FIQs. */
+	mrs	r0, cpsr
+	bic	r0, r0, #PSR_MODE
+	orr	r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE)
+	msr	cpsr, r0
+
+	/*
+	 * Set up a preliminary mapping in the MMU to allow us to run
+	 * at KERNEL_BASE with caches on.
+	 */
+	/* Build page table from scratch */
+	ldr	r0, Ltemp_l1_table
+	mov	r1, r0			/* Save the page table address. */
+	/* Zero the entire table so all virtual addresses are invalid. */
+	mov	r2, #L1_TABLE_SIZE	/* in bytes */
+	mov	r3, #0
+	mov	r4, r3
+	mov	r5, r3
+	mov	r6, r3
+	mov	r7, r3
+	mov	r8, r3
+	mov	r10, r3
+	mov	r11, r3
+1:	stmia	r1!, {r3-r8,r10-r11}
+	stmia	r1!, {r3-r8,r10-r11}
+	stmia	r1!, {r3-r8,r10-r11}
+	stmia	r1!, {r3-r8,r10-r11}
+	subs	r2, r2, #(4 * 4 * 8)	/* bytes per loop */
+	bne	1b
+
+	/* Now create our entries per the mmu_init_table. */
+	l1table	.req r0
+	va	.req r1
+	pa	.req r2
+	n_sec	.req r3
+	attr	.req r4
+	itable	.req r5
+	l1sfrm	.req r6
+	adr	itable, mmu_init_table
+	ldr	l1sfrm, Ll1_s_frame
+	b	3f
+2:	str	pa, [l1table, va]
+	add	va, va, #4
+	add	pa, pa, #(L1_S_SIZE)
+	adds	n_sec, n_sec, #-1
+	bhi	2b
+3:	ldmia	itable!, {va,pa,n_sec,attr}
+	/* Convert va to l1 offset:	va = 4 * (va >> L1_S_SHIFT)	*/
+	mov	va, va, LSR #L1_S_SHIFT
+	mov	va, va, LSL #2
+	/* Convert pa to l1 entry:	pa = (pa & L1_S_FRAME) | attr	*/
+	and	pa, pa, l1sfrm
+	orr	pa, pa, attr
+	cmp	n_sec, #0
+	bne	2b
+	.unreq	va
+	.unreq	pa
+	.unreq	n_sec
+	.unreq	attr
+	.unreq	itable
+	.unreq	l1table
+	.unreq	l1sfrm
+
+	/*
+	 * In theory, because the MMU is off, we shouldn't need all of this,
+	 * but let's not take any chances and do a typical sequence to set
+	 * the Translation Table Base.
+	 */
+	mcr	p15, 0, r0, c7, c5, 0	/* Invalidate I cache */
+1:	mrc	p15, 0, r15, c7, c14, 3	/* Test, clean, invalidate D cache. */
+	bne	1b
+	mcr	p15, 0, r0, c7, c10, 4	/* Drain the write buffers. */
+	mcr	p15, 0, r0, c2, c0, 0	/* Set Translation Table Base */
+	mcr	p15, 0, r0, c8, c7, 0	/* Invalidate TLBs */
+
+	/* Set the Domain Access register.  Very important! */
+        mov     r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
+	mcr	p15, 0, r0, c3, c0, 0
+
+	/*
+	 * Enable the MMU.
+	 */
+	ldr	r0, Lcpsr
+	mcr	p15, 0, r0, c1, c0, 0
+
+	/*
+	 * Ensure that the coprocessor has finished turning on the MMU.
+	 */
+	mrc	p15, 0, r0, c2, c0, 0	/* Read an arbitrary value. */
+	mov	r0, r0			/* Stall until read completes. */
+
+	/*
+	 * Jump to start in locore.S, which in turn will call initarm and main.
+	 */
+	ldr	pc, Lstart		/* Jump to start (flushes pipeline). */
+	/* NOTREACHED */
+
+Lstart:
+	.word	start
+Ll1_s_frame:
+	.word	L1_S_FRAME
+Ltemp_l1_table:
+	/* Put the temporary L1 translation table at the end of SDRAM. */
+	.word	KERNEL_BASE_phys + MEMSIZE_BYTES - L1_TABLE_SIZE
+Lcpsr:
+	/* What we want to have the CPSR be when we jump to start. */
+	.word CPU_CONTROL_MMU_ENABLE | \
+	      CPU_CONTROL_AFLT_ENABLE | \
+	      CPU_CONTROL_DC_ENABLE | \
+	      CPU_CONTROL_WBUF_ENABLE | \
+	      CPU_CONTROL_32BP_ENABLE | \
+	      CPU_CONTROL_32BD_ENABLE | \
+	      CPU_CONTROL_LABT_ENABLE | \
+	      CPU_CONTROL_SYST_ENABLE | \
+	      CPU_CONTROL_IC_ENABLE
+
+/* We'll modify va and pa at run time so we can use relocatable addresses. */
+#define MMU_INIT(va,pa,n_sec,attr) \
+	.word	va					    ; \
+	.word	pa					    ; \
+	.word	n_sec					    ; \
+	.word	attr					    ;
+
+mmu_init_table:
+	/* Map SDRAM where we're executing from VA==PA, read-only */
+	MMU_INIT(KERNEL_BASE_phys, KERNEL_BASE_phys,
+		1,
+		L1_S_PROTO | L1_S_AP(AP_KR))
+	/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable */
+	MMU_INIT(KERNEL_BASE, KERNEL_BASE_phys,
+		(MEMSIZE_BYTES + L1_S_SIZE - 1) / L1_S_SIZE,
+		L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C)
+	/* Map TIPB VA==PA so peripherals will work. */
+	MMU_INIT(OMAP_TIPB_PBASE, OMAP_TIPB_PBASE,
+		(OMAP_TIPB_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+		L1_S_PROTO | L1_S_AP(AP_KRW))
+	/* end of table */
+	MMU_INIT(0, 0, 0, 0)
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_nobyteacc_io.S
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_nobyteacc_io.S
@@ -0,0 +1,49 @@
+/*	$NetBSD: $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ *    and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ *    and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Byte write bus space function for 8-bit IO registers mapped on a
+ * 16-bit bus with an A0 address line.
+ */
+
+#include <machine/asm.h>
+#include <arm/armreg.h>
+
+ENTRY(nobyteacc_bs_w_1)
+	tst	r2, #1			/* even or odd byte offset? */
+	bic	r2, r2, #1		/* halfword-align offset */
+	add	r1, r1, r2		/* halfword address */
+	mrs	r2, cpsr		/* r2 = old interrupt state */
+	orr	r0, r2, #(I32_bit | F32_bit) /* interrupts off */
+	msr	cpsr, r0
+	ldrh	r0, [r1]		/* read the halfword */
+	andeq	r0, r0, #0xff00		/* even: preserve existing hi byte */
+	andeq	r3, r3, #0x00ff		/* even: mask junk in new hi byte */
+	orreq	r0, r0, r3		/* even: or in new data in lo byte */
+	andne	r0, r0, #0x00ff		/* odd:	preserve existing lo byte */
+	orrne	r0, r0, r3, lsl #8	/* odd: or data shifted to hi byte */
+	strh	r0, [r1]		/* store back halfword */
+	msr	cpsr, r2		/* restore interrupts */
+	mov	pc, lr
+
Index: netbsd_quilt/src/sys/arch/arm/omap/omap_nobyteacc_space.c
===================================================================
--- /dev/null
+++ netbsd_quilt/src/sys/arch/arm/omap/omap_nobyteacc_space.c
@@ -0,0 +1,168 @@
+/*	$NetBSD: $ */
+
+/*
+ * "nobyteacc" bus_space functions for Texas Instruments OMAP processor.
+ * Based on pxa2x0_space.c which in turn was derived from i80321_space.c.
+ *
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed for the NetBSD Project by
+ *	Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ *    or promote products derived from this software without specific prior
+ *    written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(omap);
+bs_protos(nobyteacc);
+bs_protos(generic);
+bs_protos(generic_armv4);
+bs_protos(bs_notimpl);
+
+struct bus_space nobyteacc_bs_tag = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	omap_bs_map,
+	omap_bs_unmap,
+	omap_bs_subregion,
+
+	/* allocation/deallocation */
+	omap_bs_alloc,	/* not implemented */
+	omap_bs_free,		/* not implemented */
+
+	/* get kernel virtual address */
+	omap_bs_vaddr,
+
+	/* mmap */
+	bs_notimpl_bs_mmap,
+
+	/* barrier */
+	omap_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_armv4_bs_r_2,
+	generic_bs_r_4,
+	bs_notimpl_bs_r_8,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_armv4_bs_rm_2,
+	generic_bs_rm_4,
+	bs_notimpl_bs_rm_8,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_armv4_bs_rr_2,
+	generic_bs_rr_4,
+	bs_notimpl_bs_rr_8,
+
+	/* write (single) */
+	nobyteacc_bs_w_1, /* promote 8-bit writes to 16-bit */
+	generic_armv4_bs_w_2,
+	generic_bs_w_4,
+	bs_notimpl_bs_w_8,
+
+	/* write multiple */
+	bs_notimpl_bs_wm_1,
+	generic_armv4_bs_wm_2,
+	generic_bs_wm_4,
+	bs_notimpl_bs_wm_8,
+
+	/* write region */
+	bs_notimpl_bs_wr_1,
+	generic_armv4_bs_wr_2,
+	generic_bs_wr_4,
+	bs_notimpl_bs_wr_8,
+
+	/* set multiple */
+	bs_notimpl_bs_sm_1,
+	bs_notimpl_bs_sm_2,
+	bs_notimpl_bs_sm_4,
+	bs_notimpl_bs_sm_8,
+
+	/* set region */
+	bs_notimpl_bs_sr_1,
+	generic_armv4_bs_sr_2,
+	bs_notimpl_bs_sr_4,
+	bs_notimpl_bs_sr_8,
+
+	/* copy */
+	bs_notimpl_bs_c_1,
+	generic_armv4_bs_c_2,
+	bs_notimpl_bs_c_4,
+	bs_notimpl_bs_c_8,
+};
+

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