On Fri, Apr 13, 2007 at 11:43:25PM +0900, Toru Nishimura wrote:
> Richard Earnshaw points the fact;
> 
> > No, its more to do with the memory mappings for a kernel.
> 
> I believe in that it'd be a nice exercise for CS course students to
> assess how large the whole CPU design is impacted when reset
> entry is located at other than 0 and exception entry vector can be
> populated designated paddr.

Actually the problem is with the vaddr (not paddr) of the exception
vectors (and reset entry).
For embedded systems (with no protection) address 0 is absolutely the
worst place the interrupt tabe can ever be located at.
When I did a 286 embedded board I discovered that the idt can be moved
in real mode (I tested it first, then found where it was documented).
This did, of course, stop the hw ice being used :-)

	David

-- 
David Laight: david@l8s.co.uk