On Mon, 11 Jun 2007, Jesse Off wrote:

> Likely, all you need to do is enable vsync/hsync in the control register.  On 
> FPGA bitstream load, those bits are cleared so the monitor will be in 
> power-save.  Otherwise, you'd be seeing uninitialized SDRAM until you got 
> around to zeroing out the frame buffer.

   Thanks for confirming this, works great now! :-)

   I was actually doing the HSYNC/VSYNC enable in my code already, while 
attempting to figure out where the lack of video signal came from. You're 
absolutely right -- the device memory does get mapped appropriately. The 
culprit turned out to be a nasty typo causing my SWIN register to be 2 
bytes off. :-P Assuming it's reset to zero on FPGA load, I must've been 
writing VIDCORE configuration into the UART registers. %-)

[snip]
> Not quite.  I believe the ARM pmap module (pmap_enter()) will assume any 
> physical address not explicitly registered with uvm_physload() is 
> uncacheable/unbufferable.

   Makes sense I guess, saving the startup code and drivers from having to 
register *everything* else as uncacheable.

.oO( Out of curiosity -- does this imply that it doesn't even keep track 
of what physical address regions are defined at all, for a given 
architecture? I.e. would mmap of an unused chip select area succeed, and 
silently read as bus garbage? )

Best regards,
ali:)