Re: Missing gcc arm optimization?

[Steve Woodford <scw%netbsd.org@localhost>]

On Saturday 09 February 2008 17:12:02 Chris Gilbert wrote:

> I've recently been optimizing the code on my arm-intr branch and was
> looking at the compiler output and notice it's doing something
> sub-optimal.  On the branch the splx routine looks like:

__predict_{true,false}() may well do what you want.

You also don't need to disable/enable interrupts if you're only writing 
current_ipl_level.

With those two suggestions, arm_intr_splx() becomes:

static inline void __attribute__((__unused__))
arm_intr_splx(int newspl)
{

    /* Don't reorder the assignment to current_ipl_level */
    __insn_barrier();
    current_ipl_level = newspl;
    __insn_barrier();

    /* look for interrupts at the next ipl or higher */
    if (__predict_false(ipls_pending >= (2 << newspl)))
        arm_intr_splx_lifter(newspl);

    return;
}

I think you'll find this results in much smaller asm code.

Cheers, Steve