[PATCH 5/8] TISDP2420: work around cache access breakage

[Imre Deak <imre.deak%teleca.com@localhost>]

Turning on SOSEND_NO_LOAD seems to work around an ARM cache access
bug.
---
 sys/arch/evbarm/conf/TISDP2420 |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/sys/arch/evbarm/conf/TISDP2420 b/sys/arch/evbarm/conf/TISDP2420
index 2361444..2d9a7f0 100644
--- a/sys/arch/evbarm/conf/TISDP2420
+++ b/sys/arch/evbarm/conf/TISDP2420
@@ -19,6 +19,7 @@ options       RTC_OFFSET=0    # hardware clock is this many 
mins. west of GMT
 
 options        CPU_ARM1136
 options        OMAP_2420
+options                SOSEND_NO_LOAN
 
 # Architecture options
 
-- 
1.5.6.56.g29b0d