Hi ARM folks.
I'm proud to present the NetBSD port to Marvell Armada XP[1] SoCs. The port was
done by Semihalf[2] and sponsored by Marvell, who has generously agreed to
release the source code. For a past few weeks I've been working on bringing
this port into official NetBSD source tree.
Diff against HEAD is attached to this mail. Please review it and provide
comments. I'd like to get your opinion on how to integrate it in most elegant
way.
In the meantime, enjoy the dmesg:
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 6.99.18 (ARMADAXP) #75: Sat Apr 13 16:17:32 CEST 2013
rkujawa%r2d2.home.c0ff33.net@localhost:/home/rkujawa/repos/netbsd-axp-netbsd-vanilla-head/sys/arch/evbarm/compile/obj/ARMADAXP
total memory = 2048 MB
avail memory = 2006 MB
mainbus0 (root)
cpu0 at mainbus0 core 0: Sheeva 88SV584x rev 2 (Marvell V core)
cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
cpu0: 32KB/32B 4-way L1 Instruction cache
cpu0: 32KB/32B 8-way write-back-locking-C L1 Data cache
cpu0: 2048KB/32B 32-way write-through L2 Unified cache
mvsoc0 at mainbus0: Marvell MV78460 Rev. B0 Armada XP
mvsoc0: CPU Clock 1333.000 MHz SysClock 667.000 MHz TClock 250.000 MHz
mvsoctmr0 at mvsoc0 unit 0 offset 0x20300-0x203ff irq 37: Marvell SoC Timer
com0 at mvsoc0 unit 0 offset 0x12000-0x1201f irq 41: ns16550a, working fifo
com0: console
com1 at mvsoc0 unit 1 offset 0x12100-0x1211f irq 42: ns16550a, working fifo
com2 at mvsoc0 unit 2 offset 0x12200-0x1221f irq 43: ns16550a, working fifo
com3 at mvsoc0 unit 3 offset 0x12300-0x1231f irq 44: ns16550a, working fifo
mvsocrtc0 at mvsoc0 unit 0 offset 0x10300-0x10317 irq 50: Marvell SoC Real Time
Clock
ehci0 at mvsoc0 unit 0 offset 0x50000-0x51fff irq 45: Marvell USB 2.0 Interface
usb0 at ehci0: USB revision 2.0
ehci1 at mvsoc0 unit 1 offset 0x51000-0x52fff irq 46: Marvell USB 2.0 Interface
usb1 at ehci1: USB revision 2.0
mvpex0 at mvsoc0 unit 0 offset 0x40000-0x41fff irq 58: Marvell PCI Express
Interface
pci0 at mvpex0
vendor 0x11ab product 0x7846 (miscellaneous memory, revision 0x02) at pci0 dev
0 function 0 not configured
mvpex1 at mvsoc0 unit 1 offset 0x44000-0x45fff irq 59: Marvell PCI Express
Interface
pci1 at mvpex1
mvpex2 at mvsoc0 unit 2 offset 0x48000-0x49fff irq 60: Marvell PCI Express
Interface
pci2 at mvpex2
mvpex3 at mvsoc0 unit 3 offset 0x4c000-0x4dfff irq 61: Marvell PCI Express
Interface
pci3 at mvpex3
mvpex4 at mvsoc0 unit 4 offset 0x42000-0x43fff irq 99: Marvell PCI Express
Interface
pci4 at mvpex4
vendor 0x11ab product 0x7846 (miscellaneous memory, revision 0x02) at pci4 dev
0 function 0 not configured
re0 at pci4 dev 1 function 0: RealTek 8168/8111 PCIe Gigabit Ethernet (rev.
0x06)
re0: interrupting at interrupt pin INTA#
re0: Ethernet address a0:f3:c1:00:c1:8f
rgephy0 at re0 phy 7: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 4
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
1000baseT-FDX, auto
mvpex5 at mvsoc0 unit 5 offset 0x82000-0x83fff irq 103: Marvell PCI Express
Interface
pci5 at mvpex5
vendor 0x11ab product 0x7846 (miscellaneous memory, revision 0x02) at pci5 dev
0 function 0 not configured
mvsata0 at mvsoc0 unit 0 offset 0xa0000-0xa7fff irq 55: Marvell Serial-ATA Host
Controller (SATAHC)
mvsata0: GenIIe, 1hc, 2port/hc
atabus0 at mvsata0 channel 0
atabus1 at mvsata0 channel 1
gttwsi0 at mvsoc0 unit 0 offset 0x11000-0x110ff irq 31: Marvell TWSI controller
iic0 at gttwsi0: I2C bus
spdmem0 at iic0 addr 0x56
spdmem0: DDR3 SDRAM, ECC, temp-sensor, 4GB, 1778MHz (PC3-14222)
gttwsi1 at mvsoc0 unit 1 offset 0x11100-0x111ff irq 32: Marvell TWSI controller
iic1 at gttwsi1: I2C bus
mvspi0 at mvsoc0 unit 0 offset 0x10600-0x1064f irq 30: Marvell SPI controller
spi0 at mvspi0: SPI bus
m25p0 at spi0 slave 0
spiflash0 at m25p0: Numonyx N25Q128 SPI flash
spiflash0: 16384 KB, 256 sectors of 64 KB each
mvspi1 at mvsoc0 unit 1 offset 0x10680-0x106cf irq 30: Marvell SPI controller
spi1 at mvspi1: SPI bus
uhub0 at usb0: Marvell EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub1 at usb1: Marvell EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
mvsata0 port 0: device present, speed: 3.0Gb/s
mvsata0 port 1: device present, speed: 3.0Gb/s
wd0 at atabus0 drive 0
wd0: <TS8GHSD310>
wd0: 7627 MB, 15498 cyl, 16 head, 63 sec, 512 bytes/sect x 15621984 sectors
wd1 at atabus1 drive 0
wd1: <ST980813ASG>
wd1: 76319 MB, 155061 cyl, 16 head, 63 sec, 512 bytes/sect x 156301488 sectors
boot device: <unknown>
root device: wd1a
dump device (default wd1b):
file system (default generic):
root on wd1a dumps on wd1b
root file system type: ffs
warning: no /dev/console
init path (default /sbin/init):
init: trying /sbin/init
/etc/rc.conf is not configured. Multiuser boot aborted.
Terminal type is vt100.
We recommend that you create a non-root account and use su(1) for root access.
#
The diff:
Attachment:
netbsd-head-armada-xp.diff
Description: Binary data
Additional, IO cache coherency support diff (does not work reliably on NetBSD HEAD, used to work on 6.0):
Attachment:
iocc.diff
Description: Binary data
Please cc me when replying as I'm not subscribed to port-arm. [1] http://www.marvell.com/embedded-processors/armada-xp/ [2] http://www.semihalf.com -- Best regards, Radoslaw Kujawa