[wip patch] allwinner: fix attachment of auxiliary UARTs

[Tobias Nygren <tnn%NetBSD.org@localhost>]

Hi!

I'm trying to get the physically routed aux com ports working on a
Banana Pi board. The attached patch fixes com1 and com2 attachment and
enables clock gating to the point that the ports are correctly probed
and attached.

There are a few issues though:

1) I don't understand why the third argument to bus_space_subregion in
awin_com_match needs to be divided by 4. It is already done in
awin_com_attach and com ports are not correctly probed without it.

2) timeout waiting for BUSY ack. Probably need to unmask some interrupt
somewhere. (Any clues?)

3) Should I bother to shut down the clocks in _match after probing and
re-enable them in _attach?

com0 at awinio0 port 0: ns16550a, working fifo
com0: console
com1 at awinio0 port 3: ns16550a, working fifo
com2 at awinio0 port 7: ns16550a, working fifo
[...]
root file system type: ffs
kern.module.path=/stand/evbarm/7.99.19/modules
com1: timeout while waiting for BUSY interrupt acknowledge
com2: timeout while waiting for BUSY interrupt acknowledge

Thanks,
-Tobias

Index: evbarm/conf/BPI
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/BPI,v
retrieving revision 1.14
diff -p -u -r1.14 BPI
--- evbarm/conf/BPI	21 Apr 2015 04:24:51 -0000	1.14
+++ evbarm/conf/BPI	1 Jul 2015 13:25:16 -0000
@@ -234,6 +234,8 @@ iic*		at awiniic?
 # On-board 16550 UARTs
 com0		at awinio? port 0			# UART0 (console)
 options 	CONADDR=0x01c28000, CONSPEED=115200
+#com1 at awinio? port 3 # CON3, rx pin 8 / tx pin 10
+#com2 at awinio? port 7 # J12, rx pin 4 / tx pin 6
 
 # Consumer IR
 awinir0		at awinio?
Index: arm/allwinner/awin_com.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/allwinner/awin_com.c,v
retrieving revision 1.9
diff -p -u -r1.9 awin_com.c
--- arm/allwinner/awin_com.c	7 Dec 2014 12:44:24 -0000	1.9
+++ arm/allwinner/awin_com.c	1 Jul 2015 13:25:17 -0000
@@ -130,10 +130,35 @@ awin_com_match(device_t parent, cfdata_t
 	awin_gpio_pinset_acquire(pinset);
 
 	bus_space_subregion(iot, aio->aio_core_bsh,
-	    loc->loc_offset, loc->loc_size, &bsh);
+	    loc->loc_offset / 4, loc->loc_size, &bsh);
+
+	/*
+	 * Clock gating, soft reset
+	 */
+	if (awin_chip_id() == AWIN_CHIP_ID_A80) {
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+		    AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_REG,
+		    AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0 << loc->loc_port, 0);
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+		    AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_REG,
+		    AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0 << loc->loc_port, 0);
+	} else {
+		awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+		   AWIN_APB1_GATING_REG,
+		   AWIN_APB_GATING1_UART0 << loc->loc_port, 0);
+		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+			awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
+			    AWIN_A31_APB2_RESET_REG,
+			    AWIN_A31_APB2_RESET_UART0_RST << loc->loc_port, 0);
+		}
+	}
 
 	const int rv = comprobe1(iot, bsh);
 
+	/*
+	 * XXX should we suspend the clock here and reenable it in attach?
+	 */
+
 	awin_gpio_pinset_release(pinset);
 
 	return rv;
Index: arm/allwinner/awin_reg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/allwinner/awin_reg.h,v
retrieving revision 1.78
diff -p -u -r1.78 awin_reg.h
--- arm/allwinner/awin_reg.h	3 Jun 2015 12:22:41 -0000	1.78
+++ arm/allwinner/awin_reg.h	1 Jul 2015 13:25:18 -0000
@@ -2416,6 +2416,13 @@ struct awin_mmc_idma_descriptor {
 #define AWIN_A31_APB1_RESET_DIGITAL_MIC_RST	__BIT(4)
 #define AWIN_A31_APB1_RESET_CODEC_RST		__BIT(0)
 
+#define AWIN_A31_APB2_RESET_UART5_RST		__BIT(21)
+#define AWIN_A31_APB2_RESET_UART4_RST		__BIT(20)
+#define AWIN_A31_APB2_RESET_UART3_RST		__BIT(19)
+#define AWIN_A31_APB2_RESET_UART2_RST		__BIT(18)
+#define AWIN_A31_APB2_RESET_UART1_RST		__BIT(17)
+#define AWIN_A31_APB2_RESET_UART0_RST		__BIT(16)
+
 #define AWIN_A31_APB2_RESET_TWI3_RST		__BIT(3)
 #define AWIN_A31_APB2_RESET_TWI2_RST		__BIT(2)
 #define AWIN_A31_APB2_RESET_TWI1_RST		__BIT(1)
@@ -2786,6 +2793,13 @@ struct awin_a31_dma_desc {
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_GMAC	__BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING1_USB_HOST __BIT(1)
 
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART5	__BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART4	__BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART3	__BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART2	__BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART1	__BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_UART0	__BIT(16)
+
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI4	__BIT(4)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI2	__BIT(3)
 #define AWIN_A80_CCU_SCLK_BUS_CLK_GATING4_TWI3	__BIT(2)
@@ -2798,6 +2812,13 @@ struct awin_a31_dma_desc {
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_GMAC	__BIT(17)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST1_USB_DRD	__BIT(1)
 
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART5	__BIT(21)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART4	__BIT(20)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART3	__BIT(19)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART2	__BIT(18)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART1	__BIT(17)
+#define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_UART0	__BIT(16)
+
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI4	__BIT(4)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI3	__BIT(3)
 #define AWIN_A80_CCU_SCLK_BUS_SOFT_RST4_TWI2	__BIT(2)