Re: Installation on an Orange Pi Plus 2 (Allwinner H3)

To: Robert Swindells <rjs%fdy2.co.uk@localhost>
Subject: Re: Installation on an Orange Pi Plus 2 (Allwinner H3)
From: "Yuqing.Guo.HCH" <hchguoyq%yahoo.co.jp@localhost>
Date: Sat, 24 Dec 2016 21:08:13 +0800

Hi Robert Swindells, Daniel Ziltener:

I attached the diff I made for Allwinner H3.
Please keep going with the porting.

> The main difference that I could see in the documentation for the H3
> compared to other Allwinner CPUs was the Ethernet controller.
FreeBSD support H3 now. So you may check out the FreeBSD source code.

Best wishes.
Yuqing.

On 2016年12月21日 23:33, Robert Swindells wrote:

"Yuqing.Guo.HCH" <hchguoyq%yahoo.co.jp@localhost> wrote:

I am porting NetBSD to Allwinner H3 platform(NanoPi-M1) personally, now.
The following is the dmesg, until ask the root device.
But it needs much more time to make all hardware to work,
and unfortunately I have no more free time to work with it recently.

If you don't have any more free time then maybe post some diffs of
what you have done so far and a Developer could get them into the
tree.

The main difference that I could see in the documentation for the H3
compared to other Allwinner CPUs was the Ethernet controller.

Index: sys/arch/arm/allwinner/awin_board.c
===================================================================
--- sys/arch/arm/allwinner/awin_board.c	(revision 1)
+++ sys/arch/arm/allwinner/awin_board.c	(working copy)
@@ -248,7 +248,7 @@
 	for (size_t i = 0; awin_freqs[i].freq > 0; i++) {
 		if (awin_freqs[i].freq == freq) {
 			new_awin_freq = awin_freqs[i];
-			error = 0;    
+			error = 0;
 			break;
 		}
 	}
@@ -315,7 +315,7 @@
 		if (awin_freqs[i].freq < awin_freq_min ||
 		    awin_freqs[i].freq > awin_freq_max)
 			continue;
-		snprintf(cur_cpu_freq, sizeof(cur_cpu_freq), "%u",      
+		snprintf(cur_cpu_freq, sizeof(cur_cpu_freq), "%u",
 		    awin_freqs[i].freq);
 		if (strlen(available_frequencies) > 0) {
 			strlcat(available_frequencies, " ", availfreq_size);
@@ -370,17 +370,17 @@
 	sysctl_createv(clog, 0, &freqnode, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "current", NULL,
-		       awin_current_frequency_sysctl_helper, 0, NULL, 0, 
+		       awin_current_frequency_sysctl_helper, 0, NULL, 0,
 		       CTL_CREATE, CTL_EOL);
 	sysctl_createv(clog, 0, &freqnode, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "min", NULL,
-		       NULL, 0, &awin_freq_min, sizeof(awin_freq_min), 
+		       NULL, 0, &awin_freq_min, sizeof(awin_freq_min),
 		       CTL_CREATE, CTL_EOL);
 	sysctl_createv(clog, 0, &freqnode, NULL,
 		       CTLFLAG_PERMANENT|CTLFLAG_READWRITE,
 		       CTLTYPE_INT, "max", NULL,
-		       NULL, 0, &awin_freq_max, sizeof(awin_freq_max), 
+		       NULL, 0, &awin_freq_max, sizeof(awin_freq_max),
 		       CTL_CREATE, CTL_EOL);
 }
 
@@ -398,7 +398,7 @@
 
 	ci->ci_data.cpu_cc_freq = ((uint64_t)AWIN_REF_FREQ * n) / p;
 #else
-	u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 ?
+	u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3 ?
 				      AWIN_A31_CPU_AXI_CFG_REG :
 				      AWIN_CPU_AHB_APB0_CFG_REG;
 	const uint32_t cpu0_cfg = CCM_READ4(reg);
@@ -413,7 +413,7 @@
 	case AWIN_CPU_CLK_SRC_SEL_PLL1: {
 		const uint32_t pll1_cfg = CCM_READ4(AWIN_PLL1_CFG_REG);
 		u_int p, n, k, m;
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			p = 0;
 			n = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_N) + 1;
 			k = __SHIFTOUT(pll1_cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
@@ -510,7 +510,7 @@
 {
 	CPU_INFO_ITERATOR cii;
 	struct cpu_info *ci;
-	u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 ?
+	u_int reg = awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3 ?
 				      AWIN_A31_CPU_AXI_CFG_REG :
 				      AWIN_CPU_AHB_APB0_CFG_REG;
 	int i;
@@ -612,7 +612,7 @@
 #endif
 
 #ifdef VERBOSE_INIT_ARM
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		uint32_t s[4];
 		unsigned int cpuno;
 		for (cpuno = 0; cpuno < 4; cpuno++) {
@@ -669,7 +669,7 @@
 {
 	psize_t memsize;
 
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 #ifdef VERBOSE_INIT_ARM
 		printf("memprobe not supported on A31\n");
 #endif
@@ -729,6 +729,7 @@
 	case AWIN_CHIP_ID_A20: return "A20";
 	case AWIN_CHIP_ID_A23: return "A23";
 	case AWIN_CHIP_ID_A31: return "A31";
+	case AWIN_CHIP_ID_H3:  return "H3";
 	case AWIN_CHIP_ID_A80: return "A80";
 	default: return "unknown chip";
 	}
@@ -750,7 +751,7 @@
 	 */
 	uint32_t ncfg = ocfg;
 	ncfg &= ~(AWIN_PLL_CFG_BYPASS);
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		ncfg &= ~(AWIN_PLL_CFG_FACTOR_N|AWIN_PLL_CFG_FACTOR_K);
 		ncfg |= __SHIFTIN(1, AWIN_PLL_CFG_FACTOR_K);
 		ncfg |= __SHIFTIN(24, AWIN_PLL_CFG_FACTOR_N);
@@ -765,7 +766,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL6_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL6_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL6_CFG_LOCK) == 0);
@@ -790,7 +791,7 @@
 
 	uint32_t ncfg = ocfg;
 
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		ncfg &= ~(AWIN_A31_PLL2_CFG_PREVDIV_M|
 			  AWIN_A31_PLL2_CFG_FACTOR_N|
 			  AWIN_A31_PLL2_CFG_POSTDIV_P);
@@ -811,7 +812,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL2_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL2_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL2_CFG_LOCK) == 0);
@@ -829,7 +830,7 @@
 
 	uint32_t ncfg = ocfg;
 
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		ncfg &= ~AWIN_A31_PLL3_CFG_MODE;
 		ncfg &= ~AWIN_A31_PLL3_CFG_MODE_SEL;
 		ncfg |= AWIN_A31_PLL3_CFG_FRAC_CLK_OUT;
@@ -843,7 +844,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL3_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL3_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL3_CFG_LOCK) == 0);
@@ -861,7 +862,7 @@
 
 	uint32_t ncfg = ocfg;
 
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		ncfg &= ~AWIN_A31_PLL7_CFG_MODE;
 		ncfg &= ~AWIN_A31_PLL7_CFG_MODE_SEL;
 		ncfg |= AWIN_A31_PLL7_CFG_FRAC_CLK_OUT;
@@ -875,7 +876,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL7_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL7_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL7_CFG_LOCK) == 0);
@@ -892,7 +893,7 @@
 	if (rate == 0) {
 		ncfg &= ~AWIN_PLL_CFG_ENABLE;
 	} else {
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			unsigned int m = 8;
 			unsigned int n = rate / (AWIN_REF_FREQ / m);
 			ncfg |= AWIN_A31_PLL3_CFG_MODE_SEL;
@@ -912,7 +913,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL3_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL3_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL3_CFG_LOCK) == 0);
@@ -929,7 +930,7 @@
 	if (rate == 0) {
 		ncfg &= ~AWIN_PLL_CFG_ENABLE;
 	} else {
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			unsigned int m = 8;
 			unsigned int n = rate / (AWIN_REF_FREQ / m);
 			ncfg |= AWIN_A31_PLL7_CFG_MODE_SEL;
@@ -949,7 +950,7 @@
 	if (ncfg != ocfg) {
 		CCM_WRITE4(AWIN_PLL7_CFG_REG, ncfg);
 
-		if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+		if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 			do {
 				ncfg = CCM_READ4(AWIN_PLL7_CFG_REG);
 			} while ((ncfg & AWIN_A31_PLL7_CFG_LOCK) == 0);
@@ -963,6 +964,7 @@
 	unsigned int n, k, p;
 
 	KASSERT(awin_chip_id() != AWIN_CHIP_ID_A31);
+	KASSERT(awin_chip_id() != AWIN_CHIP_ID_H3);
 	KASSERT(awin_chip_id() != AWIN_CHIP_ID_A80);
 
 	const uint32_t cfg = CCM_READ4(AWIN_PLL5_CFG_REG);
@@ -983,7 +985,7 @@
 
 	const uint32_t cfg = CCM_READ4(AWIN_PLL6_CFG_REG);
 
-	if (awin_chip_id() == AWIN_CHIP_ID_A31) {
+	if (awin_chip_id() == AWIN_CHIP_ID_A31 || awin_chip_id() == AWIN_CHIP_ID_H3) {
 		n = __SHIFTOUT(cfg, AWIN_PLL_CFG_FACTOR_N) + 1;
 		k = __SHIFTOUT(cfg, AWIN_PLL_CFG_FACTOR_K) + 1;
 		m = 2;
Index: sys/arch/arm/allwinner/awin_dma.c
===================================================================
--- sys/arch/arm/allwinner/awin_dma.c	(revision 1)
+++ sys/arch/arm/allwinner/awin_dma.c	(working copy)
@@ -89,7 +89,7 @@
 		awin_dma_a10_attach(sc, aio, loc);
 		break;
 #endif
-#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80)
+#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80) || defined(ALLWINNER_H3)
 	case AWIN_CHIP_ID_A31:
 	case AWIN_CHIP_ID_A80:
 		awin_dma_a31_attach(sc, aio, loc);
@@ -165,7 +165,7 @@
 		awin_dma_a10_dump_regs(sc);
 		break;
 #endif
-#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80)
+#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80) || defined(ALLWINNER_H3)
 	case AWIN_CHIP_ID_A31:
 	case AWIN_CHIP_ID_A80:
 		awin_dma_a31_dump_regs(sc);
Index: sys/arch/arm/allwinner/awin_dma.h
===================================================================
--- sys/arch/arm/allwinner/awin_dma.h	(revision 1)
+++ sys/arch/arm/allwinner/awin_dma.h	(working copy)
@@ -74,7 +74,7 @@
 #endif
 
 #endif
-#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80)
+#if defined(ALLWINNER_A31) || defined(ALLWINNER_A80) || defined(ALLWINNER_H3)
 void awin_dma_a31_attach(struct awin_dma_softc *, struct awinio_attach_args *,
 			 const struct awin_locators * const);
 #if defined(DDB)
Index: sys/arch/arm/allwinner/awin_io.c
===================================================================
--- sys/arch/arm/allwinner/awin_io.c	(revision 1)
+++ sys/arch/arm/allwinner/awin_io.c	(working copy)
@@ -93,6 +93,7 @@
 #define	A20	AWINIO_ONLY_A20
 #define	A31	AWINIO_ONLY_A31
 #define	A80	AWINIO_ONLY_A80
+#define	H3	AWINIO_ONLY_H3
 #define	REQ	AWINIO_REQUIRED
 
 static const struct awin_locators awin_locators[] = {
@@ -99,6 +100,7 @@
 	{ "awinicu", OFFANDSIZE(INTC), NOPORT, NOINTR, A10|REQ },
 	{ "awingpio", OFFANDSIZE(PIO), NOPORT, AWIN_IRQ_PIO, A10|A20|REQ },
 	{ "awingpio", OFFANDSIZE(PIO), NOPORT, NOINTR, A31|REQ },
+	{ "awingpio", OFFANDSIZE(PIO), NOPORT, NOINTR, H3|REQ },
 	{ "awingpio", OFFANDSIZE(A80_PIO), NOPORT, NOINTR, A80|REQ },
 	{ "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_IRQ_DMA, A10|A20 },
 	{ "awindma", OFFANDSIZE(DMA), NOPORT, AWIN_A31_IRQ_DMA, A31 },
@@ -217,6 +219,7 @@
 	const bool a10_p = chip_id == AWIN_CHIP_ID_A10;
 	const bool a20_p = chip_id == AWIN_CHIP_ID_A20;
 	const bool a31_p = chip_id == AWIN_CHIP_ID_A31;
+	const bool h3_p = chip_id == AWIN_CHIP_ID_H3;
 	const bool a80_p = chip_id == AWIN_CHIP_ID_A80;
 	prop_dictionary_t dict = device_properties(self);
 
@@ -270,6 +273,8 @@
 				continue;
 			if (a31_p && !(loc->loc_flags & AWINIO_ONLY_A31))
 				continue;
+			if (h3_p && !(loc->loc_flags & AWINIO_ONLY_H3))
+				continue;
 			if (a80_p && !(loc->loc_flags & AWINIO_ONLY_A80))
 				continue;
 		}
Index: sys/arch/arm/allwinner/awin_reg.h
===================================================================
--- sys/arch/arm/allwinner/awin_reg.h	(revision 1)
+++ sys/arch/arm/allwinner/awin_reg.h	(working copy)
@@ -189,6 +189,7 @@
 #define AWIN_SRAM_VER_KEY_A10		0x1623
 #define AWIN_SRAM_VER_KEY_A13		0x1625
 #define AWIN_SRAM_VER_KEY_A31		0x1633
+#define AWIN_SRAM_VER_KEY_H3		0x1680
 #define AWIN_SRAM_VER_KEY_A80		0x1639
 #define AWIN_SRAM_VER_KEY_A23		0x1650
 #define AWIN_SRAM_VER_KEY_A20		0x1651
@@ -1296,8 +1297,8 @@
 #define AWIN_PIO_INT_SIZE		0x0028
 
 #define AWIN_PIO_CFG_PINMASK(pin)	(7 << (4*((pin) & 7)))
-#define AWIN_PIO_DRV_MASK(pin)		((x) << (2*((pin) & 15))) 
-#define AWIN_PIO_PULn(v, pin)		((v) << (2*((pin) & 15))) 
+#define AWIN_PIO_DRV_MASK(pin)		((x) << (2*((pin) & 15)))
+#define AWIN_PIO_PULn(v, pin)		((v) << (2*((pin) & 15)))
 
 #define AWIN_PIO_FUNC_INPUT		0x0
 #define AWIN_PIO_FUNC_OUTPUT		0x1
Index: sys/arch/arm/allwinner/awin_var.h
===================================================================
--- sys/arch/arm/allwinner/awin_var.h	(revision 1)
+++ sys/arch/arm/allwinner/awin_var.h	(working copy)
@@ -41,12 +41,13 @@
 	const char *loc_name;
 	bus_size_t loc_offset;
 	bus_size_t loc_size;
-	int loc_port; 
+	int loc_port;
 	int loc_intr;
 #define	AWINIO_INTR_DEFAULT	0
 	int loc_flags;
 #define	AWINIO_REQUIRED		__BIT(8)
 #define	AWINIO_ONLY		__BITS(7,0)
+#define	AWINIO_ONLY_H3		__BIT(4)
 #define	AWINIO_ONLY_A80		__BIT(3)
 #define	AWINIO_ONLY_A31		__BIT(2)
 #define	AWINIO_ONLY_A20		__BIT(1)
@@ -101,7 +102,7 @@
 extern struct arm32_bus_dma_tag awin_coherent_dma_tag;
 
 psize_t awin_memprobe(void);
-void	awin_bootstrap(vaddr_t, vaddr_t); 
+void	awin_bootstrap(vaddr_t, vaddr_t);
 void	awin_dma_bootstrap(psize_t);
 void	awin_pll2_enable(void);
 void	awin_pll3_enable(void);
@@ -117,6 +118,7 @@
 #define AWIN_CHIP_ID_A10	AWIN_SRAM_VER_KEY_A10
 #define AWIN_CHIP_ID_A13	AWIN_SRAM_VER_KEY_A13
 #define AWIN_CHIP_ID_A31	AWIN_SRAM_VER_KEY_A31
+#define AWIN_CHIP_ID_H3		AWIN_SRAM_VER_KEY_H3
 #define AWIN_CHIP_ID_A23	AWIN_SRAM_VER_KEY_A23
 #define AWIN_CHIP_ID_A20	AWIN_SRAM_VER_KEY_A20
 #define AWIN_CHIP_ID_A80	AWIN_SRAM_VER_KEY_A80
Index: sys/arch/arm/allwinner/awin_wdt.c
===================================================================
--- sys/arch/arm/allwinner/awin_wdt.c	(revision 1)
+++ sys/arch/arm/allwinner/awin_wdt.c	(working copy)
@@ -277,6 +277,7 @@
 	switch (awin_chip_id()) {
 	case AWIN_CHIP_ID_A31:
 	case AWIN_CHIP_ID_A80:
+	case AWIN_CHIP_ID_H3:
 		off = awin_chip_id() == AWIN_CHIP_ID_A80 ?
 		    AWIN_A80_TIMER_OFFSET : AWIN_TMR_OFFSET;
 		bus_space_write_4(bst, awin_core_bsh,
Index: sys/arch/arm/allwinner/files.awin
===================================================================
--- sys/arch/arm/allwinner/files.awin	(revision 1)
+++ sys/arch/arm/allwinner/files.awin	(working copy)
@@ -26,6 +26,7 @@
 defflag opt_allwinner.h				ALLWINNER_A10: CPU_CORTEXA8
 defflag opt_allwinner.h				ALLWINNER_A20: CPU_CORTEXA7
 defflag opt_allwinner.h				ALLWINNER_A31: CPU_CORTEXA7
+defflag opt_allwinner.h				ALLWINNER_H3:  CPU_CORTEXA7
 defflag opt_allwinner.h				ALLWINNER_A80: CPU_CORTEXA7
 defflag opt_allwinner.h				AWIN_GPIO_IGNORE_FW
 defflag opt_allwinner.h				AWIN_HDMI_DEBUG
@@ -79,7 +80,7 @@
 attach	awindma at awinio with awin_dma
 file	arch/arm/allwinner/awin_dma.c		awin_dma
 file	arch/arm/allwinner/awin_dma_a10.c	awin_dma & (allwinner_a10 | allwinner_a20)
-file	arch/arm/allwinner/awin_dma_a31.c	awin_dma & (allwinner_a31 | allwinner_a80)
+file	arch/arm/allwinner/awin_dma_a31.c	awin_dma & (allwinner_a31 | allwinner_a80 | allwinner_h3)
 
 # A10/A20 TWI (IIC)
 device	awiniic : i2cbus, i2cexec, mvi2c
Index: sys/arch/evbarm/awin/awin_machdep.c
===================================================================
--- sys/arch/evbarm/awin/awin_machdep.c	(revision 1)
+++ sys/arch/evbarm/awin/awin_machdep.c	(working copy)
@@ -480,19 +480,39 @@
 	    mapallmem_p);
 
 	if (mapallmem_p) {
-		/*
-		 * "bootargs" env variable is passed as 4th argument
-		 * to kernel but it's using the physical address and
-		 * we to convert that to a virtual address.
-		 */
-		if (uboot_args[3] - AWIN_SDRAM_PBASE < ram_size) {
-			const char * const args = (const char *)
-			     (uboot_args[3] + KERNEL_BASE_VOFFSET);
-			strlcpy(bootargs, args, sizeof(bootargs));
+		if (uboot_args[0] < AWIN_SDRAM_PBASE) {
+			/* started by u-boot go command */
+#ifdef VERBOSE_INIT_ARM
+			printf("\nStarted by <u-boot go?> command.");
+#endif
+			if (uboot_args[0] > 1 && (uboot_args[1] - AWIN_SDRAM_PBASE < ram_size)) {
+				const char ** const args = (const char **)
+					(uboot_args[1] + KERNEL_BASE_VOFFSET);
+				strlcpy(bootargs, (args[1] + KERNEL_BASE_VOFFSET), sizeof(bootargs));
+			}
+
+		} else {
+			/* started by u-boot bootm command */
+#ifdef VERBOSE_INIT_ARM
+			printf("\nStarted by <u-boot bootm?> command.");
+#endif
+			/*
+			 * "bootargs" env variable is passed as 4th argument
+			 * to kernel but it's using the physical address and
+			 * we to convert that to a virtual address.
+			 */
+			if (uboot_args[3] - AWIN_SDRAM_PBASE < ram_size) {
+				const char * const args = (const char *)
+					(uboot_args[3] + KERNEL_BASE_VOFFSET);
+				strlcpy(bootargs, args, sizeof(bootargs));
+			}
 		}
-
 	}
 
+#ifdef VERBOSE_INIT_ARM
+	printf(" bootargs=<%s>\n\n", bootargs);
+#endif
+
 	boot_args = bootargs;
 	parse_mi_bootargs(boot_args);
 
@@ -651,13 +671,13 @@
 		 * XXX KLUDGE ALERT XXX
 		 * The iot mainbus supplies is completely wrong since it scales
 		 * addresses by 2.  The simpliest remedy is to replace with our
-		 * bus space used for the armcore regisers (which armperiph uses). 
+		 * bus space used for the armcore regisers (which armperiph uses).
 		 */
 		struct mainbus_attach_args * const mb = aux;
 		mb->mb_iot = &armv7_generic_bs_tag;
 		return;
 	}
- 
+
 #if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
 	if (device_is_a(self, "armgtmr")) {
 		/*
Index: sys/arch/evbarm/awin/awin_start.S
===================================================================
--- sys/arch/evbarm/awin/awin_start.S	(revision 1)
+++ sys/arch/evbarm/awin/awin_start.S	(working copy)
@@ -39,7 +39,7 @@
 #include "assym.h"
 
 #include <arm/allwinner/awin_reg.h>
-#include <evbarm/awin/platform.h>  
+#include <evbarm/awin/platform.h>
 
 RCSID("$NetBSD: awin_start.S,v 1.12 2015/04/18 11:04:49 skrll Exp $")
 
@@ -151,7 +151,7 @@
 	// Make sure the cache is flushed out to RAM for the other CPUs
 	bl	_C_LABEL(armv7_dcache_wbinv_all)
 
-#if defined(ALLWINNER_A20) || defined(ALLWINNER_A31)
+#if defined(ALLWINNER_A20) || defined(ALLWINNER_A31) || defined(ALLWINNER_H3)
 	// Read SoC ID
 	movw	r5, #:lower16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
 	movt	r5, #:upper16:(AWIN_CORE_PBASE+AWIN_SRAM_OFFSET)
@@ -189,6 +189,9 @@
 	bl	a31_mpinit
 # endif
 #endif
+#if defined(ALLWINNER_H3)
+	bl	a31_mpinit
+#endif /* ALLWINNER_H3 */
 #elif defined(ALLWINNER_A80)
 	bl	a80_mpinit
 #endif
@@ -240,13 +243,13 @@
 	dsb
 
 	/* Ensure CPU1 reset also invalidates its L1 caches */
-	ldr	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] 
+	ldr	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
 	bic	r1, r1, #(1 << 1)
 	str	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
 	dsb
 
 	/* Hold DBGPWRDUP signal low */
-	ldr	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] 
+	ldr	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG]
 	bic	r1, r1, #(1 << 1)
 	str	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG]
 	dsb
@@ -263,7 +266,7 @@
 	bl	_C_LABEL(gtmr_bootdelay)	// endian-neutral
 
 	/* Clear power-off gating */
-	ldr	r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG] 
+	ldr	r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG]
 	bic	r1, r1, #(1 << 1)
 	str	r1, [r5, #AWIN_CPUCFG_CPU1_PWROFF_REG]
 	dsb
@@ -275,7 +278,7 @@
 	dsb
 
 	/* Reassert DBGPWRDUP signal */
-	ldr	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG] 
+	ldr	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG]
 	orr	r1, r1, #(1 << 1)
 	str	r1, [r5, #AWIN_CPUCFG_DBGCTRL1_REG]
 	dsb
@@ -285,7 +288,7 @@
 #endif
 
 	//
-	// Wait up a second for CPU1 to hatch. 
+	// Wait up a second for CPU1 to hatch.
 	//
 	movw	r6, #:lower16:arm_cpu_hatched
 	movt	r6, #:upper16:arm_cpu_hatched
@@ -345,7 +348,7 @@
 	dsb
 
 	/* Ensure CPUX reset also invalidates its L1 caches */
-	ldr	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG] 
+	ldr	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
 	mov	r0, #1
 	lsl	r0, r0, r12
 	bic	r1, r1, r0
@@ -352,7 +355,30 @@
 	str	r1, [r5, #AWIN_CPUCFG_GENCTRL_REG]
 	dsb
 
+#if defined(ALLWINNER_H3)
+/***************************************************************************************************/
+/* ============================================================================== */
 	/* Release power clamp */
+	mov	r10, #0
+	mov	r1, #0xff
+	mov	r2, #0x4
+
+release_power_clamp:
+
+	lsr	r1, r1, r10
+	mul	r7, r12, r2
+	add	r7, r7, #AWIN_A31_PRCM_CPUX_PWR_CLAMP_REG
+	str	r1, [r6, r7]
+	dsb
+
+	/* continue next step */
+	add	r10, r10, #1
+	cmp	r10, #8
+	ble	release_power_clamp
+/* ============================================================================== */
+/***************************************************************************************************/
+#else
+	/* Release power clamp */
 	mov	r1, #0xe7
 	mov	r2, #0x4
 	mul	r7, r12, r2
@@ -387,13 +413,14 @@
 	ldr	r1, [r5, r7]
 	cmp	r1, #0
 	bne	1b
+#endif /* ALLWINNER_H3 */
 
 	/* We need to wait (at least) 10ms */
 	mov	r0, #0x3b000			// 10.06ms
 	bl	_C_LABEL(gtmr_bootdelay)	// endian-neutral
-	
+
 	/* Clear power-off gating */
-	ldr	r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG] 
+	ldr	r1, [r6, #AWIN_A31_PRCM_PWROFF_GATING_REG]
 	mov	r0, #1
 	lsl	r0, r0, r12
 	bic	r1, r1, r0
@@ -403,7 +430,7 @@
 	/* We need to wait (at least) 10ms */
 	mov	r0, #0x3b000			// 10.06ms
 	bl	_C_LABEL(gtmr_bootdelay)	// endian-neutral
-	
+
 	/* Bring CPUX out of reset */
 	mov	r1, #(AWIN_A31_CPUCFG_RST_CTRL_CPU_RESET|AWIN_A31_CPUCFG_RST_CTRL_CORE_RESET)
 	mov	r2, #0x40
@@ -422,7 +449,7 @@
 #endif
 
 	//
-	// Wait up a second for CPU1-3 to hatch. 
+	// Wait up a second for CPU1-3 to hatch.
 	//
 	movw	r6, #:lower16:arm_cpu_hatched
 	movt	r6, #:upper16:arm_cpu_hatched
@@ -510,7 +537,7 @@
 	bl	_C_LABEL(gtmr_bootdelay)	// endian-neutral
 
 	/* Clear power-off gating */
-	ldr	r1, [r6, #AWIN_A80_RPRCM_CLUSTER0_PWR_GATING_REG] 
+	ldr	r1, [r6, #AWIN_A80_RPRCM_CLUSTER0_PWR_GATING_REG]
 	mov	r0, #1
 	lsl	r0, r0, r12
 	bic	r1, r1, r0
@@ -546,7 +573,7 @@
 #endif
 
 	//
-	// Wait up a second for CPU1-3 to hatch. 
+	// Wait up a second for CPU1-3 to hatch.
 	//
 	movw	r6, #:lower16:arm_cpu_hatched
 	movt	r6, #:upper16:arm_cpu_hatched
Index: sys/arch/evbarm/awin/platform.h
===================================================================
--- sys/arch/evbarm/awin/platform.h	(revision 1)
+++ sys/arch/evbarm/awin/platform.h	(working copy)
@@ -37,6 +37,7 @@
 #define AWIN_hummingbird_a31	4
 #define AWIN_allwinner_a80	5
 #define AWIN_olimexlime2	6
+#define AWIN_nanopi_h3		7
 
 #include <arm/allwinner/awin_reg.h>

References:
- Installation on an Orange Pi Plus 2 (Allwinner H3)
  - From: Daniel Ziltener
- Re: Installation on an Orange Pi Plus 2 (Allwinner H3)
  - From: Yuqing.Guo.HCH
- Re: Installation on an Orange Pi Plus 2 (Allwinner H3)
  - From: Robert Swindells

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