Allwinner A10/A20 clocks

[Robert Swindells <rjs%fdy2.co.uk@localhost>]

Does the attached diff look right?

It does seem to work.

Index: sun4i_a10_ccu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/sunxi/sun4i_a10_ccu.c,v
retrieving revision 1.16
diff -u -r1.16 sun4i_a10_ccu.c
--- sun4i_a10_ccu.c	27 Jan 2021 03:10:20 -0000	1.16
+++ sun4i_a10_ccu.c	31 May 2022 01:25:02 -0000
@@ -47,6 +47,7 @@
 #define	PLL5_CFG_REG		0x020
 #define	PLL6_CFG_REG		0x028
 #define	PLL7_CFG_REG		0x030
+#define	PLL8_CFG_REG		0x040
 #define	OSC24M_CFG_REG		0x050
 #define	CPU_AHB_APB0_CFG_REG	0x054
 #define	APB1_CLK_DIV_REG	0x058
@@ -80,7 +81,7 @@
 #define	AUDIO_CODEC_SCLK_CFG_REG 0x140
 #define	LVDS_CFG_REG 		0x14c
 #define	HDMI_CLOCK_CFG_REG	0x150
-#define	MALI_CLOCK_CFG_REG	0x154
+#define	MALI_CFG_REG		0x154
 #define	IEP_SCLK_CFG_REG	0x160
 #define	CLK_OUTA_REG		0x1f0
 #define	CLK_OUTB_REG		0x1f4
@@ -114,6 +115,7 @@
 	SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30),
 	SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30),
 	SUNXI_CCU_RESET(A10_RST_LVDS, LVDS_CFG_REG, 0),
+	SUNXI_CCU_RESET(A10_RST_GPU, MALI_CFG_REG, 30),
 };
 
 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" };
@@ -126,6 +128,7 @@
 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" };
 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" };
 static const char *out_parents[] = { "losc" /* really OSC24MHz/750 */, "losc", "osc24m" };
+static const char *gpu_parents[] = { "pll_gpu" };
 
 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = {
 	{ 1008000000, 21, 1, 0, 0 },
@@ -384,6 +387,14 @@
 	SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X,
 	    "pll_video1x2", "pll_video1",
 	    1, 2),
+	SUNXI_CCU_NKMP(A10_CLK_PLL_GPU, "pll_gpu", "osc24m",
+	    PLL8_CFG_REG,		/* reg */
+	    __BITS(12, 8),		/* n */
+	    __BITS(5,4),		/* k */
+	    0,				/* m */
+	    0,				/* p */
+	    __BIT(31),			/* enable */
+	    SUNXI_CCU_NKMP_FACTOR_N_EXACT),
 
 	SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents,
 	    BE0_CFG_REG,		/* reg */
@@ -486,6 +497,13 @@
 	    __BIT(31),			/* enable */
 	    0				/* flags */
 	    ),
+	SUNXI_CCU_DIV_GATE(A10_CLK_GPU, "gpu", gpu_parents,
+	    MALI_CFG_REG,		/* reg */
+	    __BITS(3,0),		/* div */
+	    __BITS(25,24),		/* sel */
+	    __BIT(31),			/* enable */
+	    0				/* flags */
+	    ),
 
 	/* A20 specific */
 	SUNXI_CCU_NM(A20_CLK_OUT_A, "outa", out_parents,