Kyle,

Don't forget the "volatile" keyword for your h/w reference.  Multiple
references can be optimized out by the compiler.

I'll be beginning a similar effort to our 21285 h/w (currently running
our own kernel).

Here is a sample initialization sequence for enabling the uart in FIFO
mode.  This works well in our current kernel.
 

/***********************************************************************
******

	    Function:   SIO_init_uart

	    Arguments:  None

	    Returns:    Nothing

	    This function initializes the UART.  The UART is set to
operate with
	    8 bits per character, no parity, and 1 stop bit.  The UART's
timer
	    is set to cause an interrupt every 100ms.  This function is
called by
	    the function init_hardware during system startup.
	    
	    Copyright (c) 1998, CMD Technology, Inc.  Irvine, CA


************************************************************************
*****/
	typedef struct UART
	{
	    volatile u32      data;
	    volatile u32      rx_sts;
	    volatile u32      mode;
	    volatile u32      baud_hi;
	    volatile u32      baud_lo;
	    volatile u32      ctrl;
	    volatile u32      flags;
	} UART_t;

	#define UART_V_BAUD_HI       16
	#define UART_M_BAUD_LO       0xffff
	#define UART_V_MODE_DATASIZE 5
	#define UART_M_MODE_8BITS    (3 << UART_V_MODE_DATASIZE)
	#define UART_M_MODE_DEFAULT  UART_M_MODE_8BITS
	#define UART_V_CTRL_UARTEN   0
	#define UART_M_CTRL_UARTEN   (1 << UART_V_CTRL_UARTEN)

	void
	SIO_init_uart(u32 brd)
	{
	    u32 null;
		int i;
	    uart = (UART_t *) (HW_K_FOOTBRG_CONFIG_SPACE +
HW_K_FOOTBRG_UART_OFFSET);
	    irq  = (IRQ_t *)  (HW_K_FOOTBRG_CONFIG_SPACE +
HW_K_FOOTBRG_IRQ_OFFSET);

	    uart->ctrl = 0;   // Out of paranoia, make sure UART is
disabled

	    // Perform recommended init procedure, see 21285 spec (sect
6.5.2).

		// "fill" FIFO with null characters
		for (i = 0; i < 16; i++)
			uart->data = 0;

	    // Set baud rate divisor and data length (8), parity (none),
stop bits (1).
	    uart->baud_lo = (brd & UART_M_BAUD_LO);  
	    uart->baud_hi = (brd >> UART_V_BAUD_HI);
	    uart->mode = UART_M_MODE_DEFAULT;   // MUST set mode AFTER
loading baud rate

	    // Enable the UART (no seperate enable for receiver and
transmitter).
	    uart->ctrl = UART_M_CTRL_UARTEN;

		// "empty" FIFO
		for (i = 0; i < 16; i++)
		{
			null = uart->data;
			null = uart->rx_sts;
		}

	    // Enable the UART receive interrupt
	    irq->enable = IRQ_SOURCE_M_SIO_RX;
	}

	// This is a lazy put character when there is no Interrupt or
timer support.  
	// The while() is needed to prevent fifo overrun.
	void
	SIO_putc(char data)
	{
		while (uart->flags & UART_M_FLAGS_TXFULL);
		uart->data = data;
	    return;
	}

Jeffrey S. Blaalid
Dir., Network Attached Storage

CMD Technology, Inc.	Tel:  (949) 470-3155
1 Vanderbilt 	Mobile: (714) 390-8206
Irvine, CA  92618 	Fax: (949) 699-3268
mailto:blaalid@cmd.com	http://www.cmd.com



	-----Original Message-----
	From:	Kyle Mestery [SMTP:mestery@winternet.com]
	Sent:	Thursday, October 08, 1998 9:15 AM
	To:	port-arm32@netbsd.org
	Subject:	Re: Serial port question


	This didn't help.  Hmmmm.  Something else I am doing might also
be causing
	strange things to happen.  I have an unsigned int * that I set
equal to
	0x42000160, the UART address.  I then use it to print chicken
tracks
	throughout the beginning of locore.S and initarm().  Could this
be part
	of the problem?  I don't print anything after fcomcnattach() is
called.

	--
	Kyle Mestery
	StorageTek's Storage Networking Group


	On Thu, 8 Oct 1998, Kyle Mestery wrote:

	> 
	> While trying to boot my ebsa285-like hardware with NetBSD, I
noticed
	> something in footbridge_com.c that I thought was kind of
weird.  The
	> reason I noticed it was when I jump into the kernel from
firmware,
	> I seem to get to fcomcnattach() and die there, continuously
looping
	> back to this point.  I traced into this routine, and noticed
it calls
	> fcominit().  Does fcominit() have to write the UART control
register to
	> enable the FIFO?  Looking at the 21285 Core Logic sheet, the
order of
	> Serial Port initialization isn't too clear on this.  I put a
write of
	> 0x1 to the UART control register in there to see if that was
my problem.
	> I will report back as to whether or not that helped.
	> 
	> --
	> Kyle Mestery
	> StorageTek's Storage Networking Group
	> 
	>