Subject: egcs
To: None <port-arm32@netbsd.org>
From: Charles M. Hannum <root@ihack.net>
List: port-arm32
Date: 11/19/1998 23:31:24
Richard Earnshaw has graciously fixed the remaining problems I had
with egcs on the Shark. (Except for the one I mentioned before, none
of these affect NetBSD itself.) I include below all the ARM-specific
changes in my local source tree.
-----8<-----snip-----8<-----snip-----8<-----snip-----8<-----snip-----8<-----
Index: arm.c
===================================================================
RCS file: /cvsroot/src/gnu/dist/gcc/config/arm/arm.c,v
retrieving revision 1.9
diff -c -2 -r1.9 arm.c
*** arm.c 1998/11/14 04:27:17 1.9
--- arm.c 1998/11/20 04:30:05
***************
*** 214,217 ****
--- 214,227 ----
};
+ int
+ arm_preserved_register (regno)
+ int regno;
+ {
+ if (flag_pic && regno == PIC_OFFSET_TABLE_REGNUM)
+ return 1;
+
+ return ! call_used_regs[regno];
+ }
+
/* Fix up any incompatible options that the user has specified.
This has now turned into a maze. */
***************
*** 377,381 ****
if (TARGET_THUMB_INTERWORK)
for (regno = 0; regno < 16; regno++)
! if (regs_ever_live[regno] && ! call_used_regs[regno])
return 0;
--- 387,391 ----
if (TARGET_THUMB_INTERWORK)
for (regno = 0; regno < 16; regno++)
! if (regs_ever_live[regno] && arm_preserved_register (regno))
return 0;
***************
*** 383,387 ****
requires an insn */
for (regno = 16; regno < 24; regno++)
! if (regs_ever_live[regno] && ! call_used_regs[regno])
return 0;
--- 393,397 ----
requires an insn */
for (regno = 16; regno < 24; regno++)
! if (regs_ever_live[regno] && arm_preserved_register (regno))
return 0;
***************
*** 3586,3591 ****
while (from && count < max_count)
{
if (GET_CODE (from) == BARRIER)
! return from;
/* Count the length of this insn */
--- 3596,3603 ----
while (from && count < max_count)
{
+ rtx tmp;
+
if (GET_CODE (from) == BARRIER)
! found_barrier = from;
/* Count the length of this insn */
***************
*** 3595,3598 ****
--- 3607,3628 ----
&& CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
count += 8;
+ /* Handle table jumps as a single entity. */
+ else if (GET_CODE (from) == JUMP_INSN
+ && JUMP_LABEL (from) != 0
+ && ((tmp = next_real_insn (JUMP_LABEL (from)))
+ == next_real_insn (from))
+ && tmp != NULL
+ && GET_CODE (tmp) == JUMP_INSN
+ && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
+ || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
+ {
+ int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
+ count += (get_attr_length (from)
+ + GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (tmp), elt));
+ /* Continue after the dispatch table. */
+ last = from;
+ from = NEXT_INSN (tmp);
+ continue;
+ }
else
count += get_attr_length (from);
***************
*** 4750,4754 ****
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
live_regs++;
--- 4780,4784 ----
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
live_regs++;
***************
*** 4772,4776 ****
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
strcat (instr, "%|");
--- 4802,4806 ----
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
strcat (instr, "%|");
***************
*** 4869,4873 ****
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
live_regs_mask |= (1 << reg);
--- 4899,4903 ----
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
live_regs_mask |= (1 << reg);
***************
*** 4941,4945 ****
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
live_regs_mask |= (1 << reg);
--- 4971,4975 ----
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
live_regs_mask |= (1 << reg);
***************
*** 4952,4956 ****
{
for (reg = 23; reg > 15; reg--)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
floats_offset += 12;
--- 4982,4986 ----
{
for (reg = 23; reg > 15; reg--)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
floats_offset += 12;
***************
*** 4965,4969 ****
for (reg = 23; reg > 15; reg--)
{
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
floats_offset += 12;
--- 4995,4999 ----
for (reg = 23; reg > 15; reg--)
{
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
floats_offset += 12;
***************
*** 5022,5026 ****
{
for (reg = 16; reg < 24; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
reg_names[reg], REGISTER_PREFIX);
--- 5052,5056 ----
{
for (reg = 16; reg < 24; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
reg_names[reg], REGISTER_PREFIX);
***************
*** 5032,5036 ****
for (reg = 16; reg < 24; reg++)
{
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
if (reg - start_reg == 3)
--- 5062,5066 ----
for (reg = 16; reg < 24; reg++)
{
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
if (reg - start_reg == 3)
***************
*** 5202,5206 ****
if (! volatile_func)
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
live_regs_mask |= 1 << reg;
--- 5232,5236 ----
if (! volatile_func)
for (reg = 0; reg <= 10; reg++)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
live_regs_mask |= 1 << reg;
***************
*** 5240,5244 ****
{
for (reg = 23; reg > 15; reg--)
! if (regs_ever_live[reg] && ! call_used_regs[reg])
emit_insn (gen_rtx (SET, VOIDmode,
gen_rtx (MEM, XFmode,
--- 5270,5274 ----
{
for (reg = 23; reg > 15; reg--)
! if (regs_ever_live[reg] && arm_preserved_register (reg))
emit_insn (gen_rtx (SET, VOIDmode,
gen_rtx (MEM, XFmode,
***************
*** 5253,5257 ****
for (reg = 23; reg > 15; reg--)
{
! if (regs_ever_live[reg] && ! call_used_regs[reg])
{
if (start_reg - reg == 3)
--- 5283,5287 ----
for (reg = 23; reg > 15; reg--)
{
! if (regs_ever_live[reg] && arm_preserved_register (reg))
{
if (start_reg - reg == 3)
Index: arm.h
===================================================================
RCS file: /cvsroot/src/gnu/dist/gcc/config/arm/arm.h,v
retrieving revision 1.7
diff -c -2 -r1.7 arm.h
*** arm.h 1998/08/24 18:32:22 1.7
--- arm.h 1998/11/20 04:30:05
***************
*** 679,683 ****
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
! call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 0; \
} \
}
--- 679,683 ----
{ \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
! call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
} \
}
***************
*** 1183,1190 ****
{ \
for (regno = 0; regno <= 10; regno++) \
! if (regs_ever_live[regno] && ! call_used_regs[regno]) \
saved_hard_reg = 1, offset += 4; \
for (regno = 16; regno <=23; regno++) \
! if (regs_ever_live[regno] && ! call_used_regs[regno]) \
offset += 12; \
} \
--- 1183,1190 ----
{ \
for (regno = 0; regno <= 10; regno++) \
! if (regs_ever_live[regno] && arm_preserved_register (regno))\
saved_hard_reg = 1, offset += 4; \
for (regno = 16; regno <=23; regno++) \
! if (regs_ever_live[regno] && arm_preserved_register (regno))\
offset += 12; \
} \
***************
*** 2014,2017 ****
--- 2014,2018 ----
fully defined yet. */
+ int arm_preserved_register (/* int */);
void arm_override_options (/* void */);
int use_return_insn (/* void */);
Index: arm.md
===================================================================
RCS file: /cvsroot/src/gnu/dist/gcc/config/arm/arm.md,v
retrieving revision 1.1.1.5
diff -c -2 -r1.1.1.5 arm.md
*** arm.md 1998/10/14 14:29:55 1.1.1.5
--- arm.md 1998/11/20 04:30:06
***************
*** 1857,1861 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
! (clobber (reg 24))]
""
"@
--- 1857,1861 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
! (clobber (reg:CC 24))]
""
"@
***************
*** 1868,1872 ****
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
! (clobber (reg 24))]
""
"@
--- 1868,1872 ----
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
! (clobber (reg:CC 24))]
""
"@
***************
*** 4636,4640 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rI,L")]))
! (clobber (reg 24))]
""
"*
--- 4636,4640 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rI,L")]))
! (clobber (reg:CC 24))]
""
"*
***************
*** 4694,4698 ****
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg 24))]
""
"*
--- 4694,4698 ----
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
(match_operand:SI 1 "s_register_operand" "0,?r")]))
! (clobber (reg:CC 24))]
""
"*
***************
*** 4718,4722 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg 24))]
""
"*
--- 4718,4722 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC 24))]
""
"*
***************
*** 4799,4803 ****
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI")])))
! (clobber (reg 24))]
""
"*
--- 4799,4803 ----
[(match_operand:SI 1 "s_register_operand" "r")
(match_operand:SI 2 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
""
"*
***************
*** 4826,4830 ****
(match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg 24))]
""
"*
--- 4826,4830 ----
(match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
(match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
! (clobber (reg:CC 24))]
""
"*
***************
*** 4888,4893 ****
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")))
! (clobber (reg 24))]
""
"#"
--- 4888,4893 ----
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 4896,4907 ****
(define_insn "*if_plus_move"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
(plus:SI
! (match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r")
! (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L"))
! (match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m")))]
""
"@
--- 4896,4907 ----
(define_insn "*if_plus_move"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
(plus:SI
! (match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))
! (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")))]
""
"@
***************
*** 4909,4918 ****
sub%d4\\t%0, %2, #%n3
add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
! sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1
! add%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1
! sub%d4\\t%0, %2, #%n3\;ldr%D4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,4,8,8,8,8")
! (set_attr "type" "*,*,*,*,load,load")])
(define_insn "*ifcompare_move_plus"
--- 4909,4916 ----
sub%d4\\t%0, %2, #%n3
add%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
! sub%d4\\t%0, %2, #%n3\;mov%D4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,4,8,8")
! (set_attr "type" "*,*,*,*")])
(define_insn "*ifcompare_move_plus"
***************
*** 4921,4929 ****
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")
(plus:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
! (clobber (reg 24))]
""
"#"
--- 4919,4927 ----
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
(plus:SI
(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 4932,4943 ****
(define_insn "*if_move_plus"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r,r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
! (match_operand:SI 1 "arm_rhsm_operand" "0,0,?rI,?rI,m,m")
(plus:SI
! (match_operand:SI 2 "s_register_operand" "r,r,r,r,r,r")
! (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L,rI,L"))))]
""
"@
--- 4930,4941 ----
(define_insn "*if_move_plus"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 5 "cc_register" "") (const_int 0)])
! (match_operand:SI 1 "arm_rhs_operand" "0,0,?rI,?rI")
(plus:SI
! (match_operand:SI 2 "s_register_operand" "r,r,r,r")
! (match_operand:SI 3 "arm_add_operand" "rI,L,rI,L"))))]
""
"@
***************
*** 4945,4954 ****
sub%D4\\t%0, %2, #%n3
add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
! sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1
! add%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1
! sub%D4\\t%0, %2, #%n3\;ldr%d4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,4,8,8,8,8")
! (set_attr "type" "*,*,*,*,load,load")])
(define_insn "*ifcompare_arith_arith"
--- 4943,4950 ----
sub%D4\\t%0, %2, #%n3
add%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
! sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,4,8,8")
! (set_attr "type" "*,*,*,*")])
(define_insn "*ifcompare_arith_arith"
***************
*** 4963,4967 ****
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rI")])))
! (clobber (reg 24))]
""
"#"
--- 4959,4963 ----
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 4992,4997 ****
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")))
! (clobber (reg 24))]
""
"*
--- 4988,4993 ----
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_rhs_operand" "rI,rI")])
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
! (clobber (reg:CC 24))]
""
"*
***************
*** 5018,5027 ****
output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands);
if (which_alternative != 0)
! {
! if (GET_CODE (operands[1]) == MEM)
! return \"ldr%D6\\t%0, %1\";
! else
! return \"mov%D6\\t%0, %1\";
! }
return \"\";
"
--- 5014,5018 ----
output_asm_insn (\"%I7%d6\\t%0, %4, %5\", operands);
if (which_alternative != 0)
! return \"mov%D6\\t%0, %1\";
return \"\";
"
***************
*** 5030,5048 ****
(define_insn "*if_arith_move"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI (match_operator 4 "comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
(match_operator:SI 5 "shiftable_operator"
! [(match_operand:SI 2 "s_register_operand" "r,r,r")
! (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")])
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m")))]
""
"@
%I5%d4\\t%0, %2, %3
! %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1
! %I5%d4\\t%0, %2, %3\;ldr%D4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,8,8")
! (set_attr "type" "*,*,load")])
(define_insn "*ifcompare_move_arith"
--- 5021,5038 ----
(define_insn "*if_arith_move"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI (match_operator 4 "comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
(match_operator:SI 5 "shiftable_operator"
! [(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))]
""
"@
%I5%d4\\t%0, %2, %3
! %I5%d4\\t%0, %2, %3\;mov%D4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,8")
! (set_attr "type" "*,*")])
(define_insn "*ifcompare_move_arith"
***************
*** 5051,5059 ****
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rIm")
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg 24))]
""
"*
--- 5041,5049 ----
[(match_operand:SI 4 "s_register_operand" "r,r")
(match_operand:SI 5 "arm_add_operand" "rIL,rIL")])
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
(match_operator:SI 7 "shiftable_operator"
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
! (clobber (reg:CC 24))]
""
"*
***************
*** 5081,5090 ****
if (which_alternative != 0)
! {
! if (GET_CODE (operands[1]) == MEM)
! output_asm_insn (\"ldr%d6\\t%0, %1\", operands);
! else
! output_asm_insn (\"mov%d6\\t%0, %1\", operands);
! }
return \"%I7%D6\\t%0, %2, %3\";
"
--- 5071,5075 ----
if (which_alternative != 0)
! output_asm_insn (\"mov%d6\\t%0, %1\", operands);
return \"%I7%D6\\t%0, %2, %3\";
"
***************
*** 5093,5112 ****
(define_insn "*if_move_arith"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
! (match_operand:SI 1 "arm_rhsm_operand" "0,?rI,m")
(match_operator:SI 5 "shiftable_operator"
! [(match_operand:SI 2 "s_register_operand" "r,r,r")
! (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI")])))]
""
"@
%I5%D4\\t%0, %2, %3
! %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1
! %I5%D4\\t%0, %2, %3\;ldr%d4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,8,8")
! (set_attr "type" "*,*,load")])
(define_insn "*ifcompare_move_not"
--- 5078,5096 ----
(define_insn "*if_move_arith"
! [(set (match_operand:SI 0 "s_register_operand" "=r,r")
(if_then_else:SI
(match_operator 4 "comparison_operator"
[(match_operand 6 "cc_register" "") (const_int 0)])
! (match_operand:SI 1 "arm_rhs_operand" "0,?rI")
(match_operator:SI 5 "shiftable_operator"
! [(match_operand:SI 2 "s_register_operand" "r,r")
! (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))]
""
"@
%I5%D4\\t%0, %2, %3
! %I5%D4\\t%0, %2, %3\;mov%d4\\t%0, %1"
[(set_attr "conds" "use")
! (set_attr "length" "4,8")
! (set_attr "type" "*,*")])
(define_insn "*ifcompare_move_not"
***************
*** 5119,5123 ****
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg 24))]
""
"#"
--- 5103,5107 ----
(not:SI
(match_operand:SI 2 "s_register_operand" "r,r"))))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5149,5153 ****
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg 24))]
""
"#"
--- 5133,5137 ----
(match_operand:SI 2 "s_register_operand" "r,r"))
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5180,5184 ****
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg 24))]
""
"#"
--- 5164,5168 ----
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
(match_operand:SI 1 "arm_not_operand" "0,?rIK")))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5213,5217 ****
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
! (clobber (reg 24))]
""
"#"
--- 5197,5201 ----
[(match_operand:SI 2 "s_register_operand" "r,r")
(match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5248,5252 ****
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rM")])))
! (clobber (reg 24))]
""
"#"
--- 5232,5236 ----
[(match_operand:SI 3 "s_register_operand" "r")
(match_operand:SI 4 "arm_rhs_operand" "rM")])))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5280,5284 ****
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])))
! (clobber (reg 24))]
""
"#"
--- 5264,5268 ----
[(match_operand:SI 2 "s_register_operand" "r")
(match_operand:SI 3 "arm_rhs_operand" "rI")])))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 5310,5314 ****
(match_operand:SI 3 "arm_rhs_operand" "rI")])
(not:SI (match_operand:SI 1 "s_register_operand" "r"))))
! (clobber (reg 24))]
""
"#"
--- 5294,5298 ----
(match_operand:SI 3 "arm_rhs_operand" "rI")])
(not:SI (match_operand:SI 1 "s_register_operand" "r"))))
! (clobber (reg:CC 24))]
""
"#"
***************
*** 6103,6107 ****
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg 24))]
"reload_completed"
[(set (match_dup 6) (match_dup 7))
--- 6087,6091 ----
(match_operand 4 "" "")
(match_operand 5 "" "")))
! (clobber (reg:CC 24))]
"reload_completed"
[(set (match_dup 6) (match_dup 7))
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