Hi,

On Fri, 06 Oct 2000, Alstrup, Kurt wrote:
> I am about to do an attempt to port the NetBSD OS to an IXP1200 processor,
> which contains an SA-1100 compatiple CPU core.

Does it have no MMU then?

[snip stuff I don't know about]

>  - The footbridge co-processor maps the ROM (a flash device on CATS) to
> address 0 until first write (to what I'm not sure) whereafter the SDRAM
> will be visible on address 0. The IXP1200 does not have that capability, so
> can I put a ROM device at address 0 permanently and have the RAM at eg
> c000:0000 ?

Checking an arm ref book I have handy says that the 0 address contains an 
unconditional branch instruction to the relevant exeception handler, the 
exceptions and table look like:
Address		Exception vector
&00		Reset
&04		Undefined Instruction
&08		Software Interrupt
&0C		Abort (prefetch)
&10		Abort (data)
&14		Reserved
&18		IRQ
&1C		FIQ

You can probably find more details online from somewhere, or in the arm32 
code.  Hardest part maybe getting from the ROM exeception handlers into 
runtime RAM based ones.  But then perhaps you can cheat, and have in the rom 
exception code a look up of an address in RAM, and check if it's 0 (but then 
if the machine has just started up you don't know that the instruction will 
contain 0, but then if you can avoid doing any exceptions it might just work 
;)

Cheers,
Chris