Subject: Re: Possible bug in arm32 strongarm optimisations.
To: David Brownlee <abs@netbsd.org>
From: Mike Pumford <mpumford@mpc-data.co.uk>
List: port-arm32
Date: 10/26/2000 15:47:36
> On Thu, 26 Oct 2000, David Brownlee wrote:
> =
> Just a thought on this - how much of a gain would it be for
> StrongARM RiscPC machines to be able to use the non halfword
> StrongARM instructions? Would there be any sense in adding another
> -march or similar option to gcc?
> =
I think that is what -march=3Darmv3m means. It allows the use of the =
enhanced multiply instructions but inhibits the halfword load/store =
instructions. The -mtune=3Dstrongarm option enables the instruction =
reordering to reduce result register dependencies.
Last time I tried the performance differences were not really noticable =
and compiling userland with these options eventually led to some weird =
anomolies with config. Given that some compiler issues have now been =
resolved It might be worth another go now.
Mike