On Wed, Dec 20, 2000 at 05:24:34PM +0000, Ben Harris wrote:

 > That can be handled (function pointers are easy), as can the different
 > exception handling (you'd need two versions of zero page).
 > 
 > > not to 
 > > mention the fact that in 26-bit mode you have to be much more careful 
 > > about using "movs pc,..." in the right places, and not using the msr or 
 > > mrs instructions.  We'd practically end up with two of everything.
 > 
 > Once we get GCC to emit mode-neutral APCS-32 code, all the C code would be
 > dealt with.  There are a few parts of locore which would need to switch on
 > CPU type, but that's known technology.  All the tedious bits of the kernel
 > (VM, filesystems, networking) would share quite happily.  It's not a
 > sensible thing to do, but it indicates that "theoretically possible" isn't
 > the best guide.

It sounds like what we need is:

	sys/arch/arm
	sys/arch/arm/arm	<- shared by all arm cpus
	sys/arch/arm/arm32	<- arm32 cpus
	sys/arch/arm/arm26	<- arm26 cpus

...and then:

	sys/arch/hpcarm32	<- hpcarm32 port
	sys/arch/dnard		<- dnard port

...etc.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>