On Fri, 5 Jan 2001, Richard Earnshaw wrote:

> Here's some that are in the ARM ARM that I have

Thanks.  I really must get an ARM ARM.

> Neither the 7500 nor the 7500FE data sheets seem to document the CPU id -- 
> Odd.

Yes.  I think one of the data sheets I looked at even said that the ID
register was unpredicatable on read.

> The format of the ID register is quite complex, but it can be decoded with 
> care.  Here's what the ARM ARM says (I've tried to summarise a bit, since 
> it is quite long)

Thanks.  That lot all seems to fit the IDs I've got here, which is better
than anything else I've found.

> [19:16] Architecture code.  Following values are currently defined, all 
> others reserved.
>    0x1 ARMv4
>    0x2 ARMv4T
>    0x3 ARMv5
>    0x4 ARMv5T

The 80200 and the ARM966E-S rev. 1 seem to have 5 here.  The 80200 claims
to implement ARMv5TE.  Is that a sensible meaning for it?

-- 
Ben Harris                                                   <bjh21@netbsd.org>
Portmaster, NetBSD/arm26               <URL:http://www.netbsd.org/Ports/arm26/>