On Tuesday 06 March 2001 10:38 am, Richard Earnshaw wrote:
> However, ARMv5 does mandate that all use of NV takes the undefined
> instruction trap, except where new instructions have been defined for that
> space.

Ahh, I should really look more closely at what these new instructions are, 
but lack of time...

> BTW, the old NV condition code took up 1/16th of the entire opcode space
> on the ARM; it represents probably the largest chunk of unallocated
> instructions in the ARM instruction space.  It was obsoleted in ARMv3 and
> so it now makes good sense to use it for extending the architecture; so I
> would expect to see more and more instructions added in this area.

True, aslong as it's not grow into some of the other "RISC" processors with 
hundreds of instructions...

> NB. the code in question could be made safer by adding a check for the cpu
> class (which could be set up during boot).

Yep, I suppose the way to do it is to have an arm7 swi handler, just be a 
matter of setting up the zero page differently.

Cheers,
Chris
PS apologies for the tone of this mornings email, got out of bed on the wrong 
side