On Sunday 01 April 2001  9:37 pm, Chris Gilbert wrote:
> On Sunday 01 April 2001  4:44 pm, IWAMOTO Toshihiro wrote:
> > (I hope this patch is also useful on hpcarm, but cache miss penalty is
> > quite high there, at least for my jornada720.  lmbench says it takes
> > 300ns to load a cache line...)
>
> It should be useable elsewhere, but I've not investigated the irq handling
> on other systems yet.  I've only got access to a riscpc, but I do believe
> that the core code will be similiar.

Having looked at the irq handlers in:
hpcarm/sa11x0/sa11x0_irq.S
footbridge/footbridge_irq.s (something I noticed is that I don't think 
multiple handlers for the same irq's will work properly on footbridge)
isa/isa_irq.S
ofw/ofw_irq.S (although I'm not quite sure why but it looks to only get 
called by the timer...)
they all have common code, IE they all get the irq request into r8, and then 
use identical (sa11x0 has some debug #ifdef's in) to service the interrupt.

I'll try and find time to make a patch up for the above (assuming that people 
out there have the relevant hardware to test on)  it'd be great if I could 
manage to merge them all. it would end up with one file with lots of #ifdef's 
at the top.  But perhaps that'd be better than having 5 files with a section 
of identical code that all need altering if any change to the irq handling 
happens.

Cheers,
Chris