> On Thu, 24 May 2001, Ignatios Souvatzis wrote:
> 
> > On Thu, May 24, 2001 at 11:22:51AM +0100, Richard Earnshaw wrote:
> > > No, because by the time the fault happens you no-longer know where the
> > > faulty instruction is.
> > >
> > > Remember the problem occurs when
> > >
> > > 1) The last instruction in the page is ldr or ldm that writes the PC
> > > 2) The next page is not mapped
> >
> > Evil idea: "always map the next page when the last longword is a ldr or ldm
> > that writes the PC."
> >
> > Of course, an option.
> > Wasn't somebody rewriting the pmap?
> 
> 	I think the only clean guaranteed way to avoid the problem would
> 	be to have a compiler option to use the instructions to load the
> 	individual registers. 
Which would bugger up performance for everybody.  Only 0.1% of the LDM 
instructions are likely to be on the end of a page (4k page 4b 
instruction), but we would have to fix all of them since we don't know 
where they will get linked.

> A more complex variation would be to handle
> 	it in the linker based on the alignment of the instruction insert
> 	a nop to shift the ldm to the next page.

Which would break internal offset calculations.

> 
> 	Of course given the small number of machines with that hardware
> 	it may be difficult to get it back into the gcc mainline.

Well I wouldn't support such changes, particularly in the mainline GCC,... 
(but I'm not the only maintainer ...)  I don't think hacking the compiler 
is the right way to solve this problem (which is why I wrote fix4SArev2 in 
the first place...)

R.