On Thu, 24 May 2001, Richard Earnshaw wrote:

> > 	I think the only clean guaranteed way to avoid the problem would
> > 	be to have a compiler option to use the instructions to load the
> > 	individual registers.
> Which would bugger up performance for everybody.  Only 0.1% of the LDM
> instructions are likely to be on the end of a page (4k page 4b
> instruction), but we would have to fix all of them since we don't know
> where they will get linked.
>
> > A more complex variation would be to handle
> > 	it in the linker based on the alignment of the instruction insert
> > 	a nop to shift the ldm to the next page.
>
> Which would break internal offset calculations.
>
> >
> > 	Of course given the small number of machines with that hardware
> > 	it may be difficult to get it back into the gcc mainline.
>
> Well I wouldn't support such changes, particularly in the mainline GCC,...
> (but I'm not the only maintainer ...)  I don't think hacking the compiler
> is the right way to solve this problem (which is why I wrote fix4SArev2 in
> the first place...)

	Variation on the theme (which I'm sure we have been around before)
	Have an option to write all LDMs as a LDM+NOP, then have the
	linker swap them around if on the end of a page.

	This would have to be a compiler option that defaulted to off :)

-- 
		David/absolute		-- www.netbsd.org: No hype required --