PCI interrupt settings

[KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>]

Hi! all, (?)


I know the mistake is found in the interrupt setting of PCI.  It is not
implemented at all.  I had it correspond to present interrupt based on
the source of 3.1.
In present interrupt, 32 BeInterruptController queues up following
i8259(16).

However, this doesn't confirm to work surely.  After it is confirmed
that PCI works correctly, this correction will commit. 

Thanks,
--
kiyohara

Index: pci/pci_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/bebox/pci/pci_machdep.c,v
retrieving revision 1.15
diff -u -r1.15 pci_machdep.c
--- pci/pci_machdep.c   17 Oct 2007 19:54:05 -0000      1.15
+++ pci/pci_machdep.c   8 Feb 2008 16:59:13 -0000
@@ -105,7 +105,17 @@
 bebox_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin,
     int swiz, int *iline)
 {
-#if 0
-       (*platform->pci_intr_fixup)(bus, dev, iline);
-#endif
+
+       if (bus == 0) {
+               switch (dev) {
+               case 12: /*       SCSI is bit 10, mapped to IRQ 26 */
+               case 13: /* PCI slot 1 is bit 11, mapped to IRQ 27 */
+               case 14: /* PCI slot 2 is bit 12, mapped to IRQ 28 */
+               case 15: /* PCI slot 3 is bit 13, mapped to IRQ 29 */
+#define  BEBOX_PCIBUS0_DEV2LINE(d)     ((d) + 14)
+                       *iline = BEBOX_PCIBUS0_DEV2LINE(dev);
+               }
+       } else
+#define  BEBOX_PCIBUS_DEV2LINE(d, s)   ((((d) + (s) + 1) & 0x3) + 26)
+               *iline = BEBOX_PCIBUS_DEV2LINE(dev, swiz);
 }