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Hi,

I've been trying to work-around a bug with the ABLE BIOS for cats.  The
issue is that ABLE enables native mode on the aceride chipset.  However,
it fails to put in place any of the interrupt routing, IE it doesn't
setup the interrupts to route out onto the PCI bus or internally to isa
interrupts.

I've considered different way to workaround this, eg fix up the routing,
 detect broken routing and disable Native mode etc.  However even with
fixed routing the secondary channel doesn't work as it's not on the same
IRQ as the primary, and the IDE code assumes it will be.

I think the best thing to do is to force the chipset back to compat mode
with a flag.

To this end I've taken the next spare flag for PCIIDE, and used it to
indicate that the aceride should be using compat mode.

This then allows control from the config file, so in cats config files
we can workaround the BIOS issue.

Attached is a diff (including man page update) to use a flag to do this.
 The change to the config file is to just tag a flags value on the end:
aceride*        at pci? dev ? function ? flags 0x0004   # Acer Lab IDE
controllers

Does this look ok?  I'd like to check in the chage in then next couple
of days.

Thanks,
Chris

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Index: share/man/man4/aceride.4
===================================================================
RCS file: /cvsroot/src/share/man/man4/aceride.4,v
retrieving revision 1.2
diff -u -p -r1.2 aceride.4
--- share/man/man4/aceride.4	8 Oct 2003 13:39:11 -0000	1.2
+++ share/man/man4/aceride.4	29 Aug 2007 09:06:33 -0000
@@ -49,6 +49,13 @@ driver to disable DMA on chipsets for wh
 enabled.
 This can be used as a debugging aid, or to work around
 problems where the IDE controller is wired up to the system incorrectly.
+.Pp
+The 0x0004 flag forces the
+.Nm
+driver to disable Native mode on chipsets for which Native mode would
+normally be enabled.
+This can be used to work around problems where the BIOS has not configured
+mappings for the native interrupts.
 .Sh SEE ALSO
 .Xr ata 4 ,
 .Xr atapi 4 ,
Index: sys/dev/pci/pciidevar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciidevar.h,v
retrieving revision 1.35
diff -u -p -r1.35 pciidevar.h
--- sys/dev/pci/pciidevar.h	17 Oct 2006 13:45:05 -0000	1.35
+++ sys/dev/pci/pciidevar.h	29 Aug 2007 09:06:33 -0000
@@ -47,6 +47,7 @@
 /* options passed via the 'flags' config keyword */
 #define	PCIIDE_OPTIONS_DMA	0x01
 #define	PCIIDE_OPTIONS_NODMA	0x02
+#define	PCIIDE_OPTIONS_FORCE_COMPAT	0x04
 
 #ifndef ATADEBUG
 #define ATADEBUG
Index: sys/dev/pci/aceride.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/aceride.c,v
retrieving revision 1.23
diff -u -p -r1.23 aceride.c
--- sys/dev/pci/aceride.c	9 Feb 2007 21:55:27 -0000	1.23
+++ sys/dev/pci/aceride.c	29 Aug 2007 09:06:33 -0000
@@ -167,7 +167,14 @@ acer_chip_map(struct pciide_softc *sc, s
 	    ~ACER_CHANSTATUSREGS_RO);
 	cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG);
 	cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT);
+	
+	if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
+                    PCIIDE_OPTIONS_FORCE_COMPAT)
+		cr &= ~((PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))
+				<< PCI_INTERFACE_SHIFT);
+
 	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr);
+
 	/* Don't use cr, re-read the real register content instead */
 	interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag,
 	    PCI_CLASS_REG));

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