Hi,
I've looked at the sources and from what I get the port handles virtual
memory by means of TLB miss exceptions and software address translation?
I looked in InitSH3() but I don't understand how the page dir thing works?
How does the SH4 handle the data pointed to by TTB?
From what I gather of what the h/w manual says, the MMU will first search
the UTLB for a match and then (if no match was found) the data pointed to by
TTB will be searched and if a match was found it'll get cached into the
UTLB?

Thankful for help,
--scav