Re: Address space limit?

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

> I've been told that this might be an issue with the m68k pmap code
> allocating only one page for the page table, and assuming the page
> table is contiguous. Any suggestions on a workaround?

One trivial workaround is to use 8KB/page settings:

Index: include/param.h
===================================================================
RCS file: /cvsroot/src/sys/arch/hp300/include/param.h,v
retrieving revision 1.53
diff -u -p -d -r1.53 param.h
--- include/param.h	10 Feb 2012 17:35:49 -0000	1.53
+++ include/param.h	10 Jan 2019 15:46:06 -0000
@@ -47,7 +47,7 @@
 #define	_MACHINE	hp300
 #define	MACHINE		"hp300"
 
-#define	PGSHIFT		12		/* LOG2(NBPG) */
+#define	PGSHIFT		13		/* LOG2(NBPG) */
 #define	KERNBASE	0x00000000	/* start of kernel virtual */
 
 #define	UPAGES		2		/* pages of u-area */


---

This will allow 960 MB VA space, instead of 224 MB.


Details:

Note this m68k pmap restriction is affected only for 68040/060 machines.
src/sys/arch/m68k/include/pmap_motorola.h says:
---
 * MMU specific segment values
 *
 * We are using following segment layout in m68k pmap_motorola.c:
 * 68020/030 4KB/page: l1,l2,page    == 10,10,12	(%tc = 0x82c0aa00)
 * 68020/030 8KB/page: l1,l2,page    ==  8,11,13	(%tc = 0x82d08b00)
 * 68040/060 4KB/page: l1,l2,l3,page == 7,7,6,12	(%tc = 0x8000)
 * 68040/060 8KB/page: l1,l2,l3,page == 7,7,5,13	(%tc = 0xc000)
 *
 * 68020/030 l2 size is chosen per NPTEPG, a number of page table entries
 * per page, to use one whole page for PTEs per one segment table entry,
 * and maybe also because 68020 HP MMU machines use simlar structures.
 *
 * 68040/060 layout is defined by hardware design and not configurable,
 * as defined in <m68k/pte_motorola.h>.
 *
 * Even on 68040/060, we still appropriate 2-level ste-pte pmap structures
 * for 68020/030 (derived from 4.4BSD/hp300) to handle 040's 3-level MMU.
 * TIA_SIZE and TIB_SIZE are used to represent such pmap structures and
 * they are also refered on 040/060.
---

On 4KB/page settings:
- l1 page is allocated at the first 512 bytes of the L1 page
  of the 2-level ste-pte pmap stractures
- l2 page is allocated at the rest (4096 - 512) bytes of the L1 page

Only 7 l2 are allocated and they have 896 (== (512 / 4) * 7) entries.
Then VA space is limited upto 224 MB (== 896 * (256(l3) / 4) * 4096).

On 8KB/page settings:
- l1 page is allocated at the first 512 bytes of the L1 page
  of the 2-level ste-pte pmap stractures
- l2 page is allocated at the rest (8192 - 512) bytes of the L1 page

This allow 15 l2 and they have 1920 (== (512 / 4) * 15) entries.
Then VA space limit is upto 960 MB (== 1920 * 256(l3) / 4) * 8192).

This is the longstanding issue of NetBSD/m68k pmap,
but currently less activities, unfortunately.

---
Izumi Tsutsui