Hi,

I'm working on NEC's new MIPS CPU Vr4131.

Vr4131 has 2-way set-associative cache though Vr4131's 
processor revision number on COP0 is same as other 
Vr41xx which has direct-mapped cache. So, you must
distinguish Vr4131 from other Vr41xx in mips_config_cache().
You can use highest bit of MIPS_PRID_REV field.

I've made the patch (attached). I'd like to commit the patch
if no one objects.

Takemura

sys/arch/mips/mips/cache.c:

mips_config_cache(void)
{
        /*
         * Configure primary caches.
         */
        switch (MIPS_PRID_IMPL(cpu_id)) {
<snipped>
        case MIPS_R4000:
        case MIPS_R4100:
        case MIPS_R4300:
+ #ifdef MIPS3_4100
+               /*
+                * Vr4131 has cpu_id=0x0c80
+                * and R4600 style 2-way set-associative cache
+                */
+               if (!(MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
+                   (MIPS_PRID_REV(cpu_id) & 0x80))) {
+ #endif
                mips_picache_ways = 1;
                mips_pdcache_ways = 1;
<snipped>
                /* Virtually-indexed cache; no use for colors. */
                break;
+ #ifdef MIPS3_4100
+               }
+               /* fall through if CPU is Vr4131 */
+ #endif

        case MIPS_R4600:
        case MIPS_RM5200:
                mips_picache_ways = 2;
                mips_pdcache_ways = 2;

EOF