Could folks that know for sure that various models of MIPS cpus _don't_
support the LL & SC instructions please update the table we have that
describes CPU cababilities?  This involves adding the CPU_MIPS_NO_LLSC
flag in the cputab in sys/arch/mips/mips/mips_machdep.c.

Currently the MIPS1 cpus and the R5900 are listed; I know that some of
the CPUs used in the HPCMIPS devices don't support LL/SC, but I'm not
100% sure which ones...

Thanks,
Simon.
--
Simon Burge                                   <simonb@wasabisystems.com>
NetBSD Development, Support and Service:   http://www.wasabisystems.com/