Subject: Re: Clio Patches...
To: None <port-hpcmips@NetBSD.org>
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
List: port-hpcmips
Date: 03/26/2006 13:54:21
In article <Pine.BSF.4.51.0603251955370.34152@vegeta.city-net.com>
darkstar@city-net.com wrote:

> My
> understanding is that the tripad hardware layout is identical to the
> C-1000 internally, however I don't have one.

Could anyone confirm this?
If not, I'll change only lines for tripad for now.

> > > allows use of dbsym,
> >
> > I'm not familiar with hpcmips, but doesn't pbsdboot load
> > symbol table? If so, shouldn't we check if bootinfo is
> > processed properly first rather than just using dbsym(8)?
> 
>   It doesn't work.  I don't have any way of building pbsdboot so I didn't
> look at why.  I sent port-hpcmips/26426 about this and included this patch
> as a workaround.  The patch uses the loaded symbols if present (if
> pbsdboot is set to load symbols then dbsym will not work and the symbol
> loading does not work either).

dbsym(8) is just a workaround for ports which don't have native
bootloader that can load symbols. If it doens't work, why don't
you try to fix it rather than hide it by ugly workaround? ;-p

At least you could confirm if bootinfo is passed correctly or not
by options DEBUG, and maybe you should mention what version of
pbsdboot or hpcboot you use. Even if you still want to use dbsym(8),
it should be wrapped by #ifdef SYMTAB_SPACE.

> > > fixes delay
> > > time on the VR4111,
> >
> > Do you have any article, errata or measurement for us
> > to confirm this?
> 
>   I noticed it with cycle counter tests of delay time while working on my
> updated slhci driver, but I don't know any Nec documentation mentioning
> the correction.  Later VR series CPUs all are documented to have two clock
> branch delays.  Earlier VR series CPUs had a single clock delay, so I
> would guess it was just overlooked in creating the 4111 manual.

According to VR4111 and VR4121 manuals, they have completely
differnt pipeline structures (see chapter 5 VR41[12]1 pipeline).
I don't think there is any possible overlooking around
figures of pipeline activities (figure 5-3 in VR4111 manual
and figure 5-5 in VR4121 one), so I'll leave this part.
---
Izumi Tsutsui